ADS5510
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SLAS499–JANUARY 2007
Table 2. Serial Register Table(1)
A3 A2 A1 A0 D11
D10
D9
D8 D7 D6 D5 D4 D3 D2
D1
D0
DESCRIPTION
DLL
CTRL
Clock DLL
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Internal DLL is on; recommended for 60 MSPS to 125 MSPS
clock speeds.
Internal DLL is off; recommended for 2 MSPS to 80 MSPS
clock speeds.
TP<1> TP<0>
Test Mode
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
Normal mode of operation
All outputs forced to 0
All outputs forced to 1
0
(2)(3)
0
Each output bit toggles between 0 and 1.
PDN
0
Power Down
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
0
0
Normal mode of operation
1
Device is put in power-down (low-current) mode.
(1) The register contents default to the appropriate setting for normal operation up on RESET.
(2) The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test mode
outputs will be the binary two's complement equivalent of these patterns as described in the Output Information section.
(3) While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D10. For
example, when D0 is a 1, D1 in not assured to be a 0, and vice versa.
Table 3. Data Format Select (DFS) Table
DFS-PIN VOLTAGE (VDFS
)
DATA FORMAT
CLOCK OUTPUT POLARITY
2
12
Straight Binary
Data valid on rising edge
V
t
AV
DD
DFS
5
12
4
12
Two's Complement
Straight Binary
Data valid on rising edge
Data valid on falling edge
Data valid on falling edge
AV
AV
u
t V
t
AV
AV
DD
DD
DFS
8
12
7
12
t V
t
DD
DD
DFS
10
12
Two's Complement
V
AV
DD
DFS
9
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