ADS5510
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SLAS499–JANUARY 2007
TIMING CHARACTERISTICS(1)(2)
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD
DRVDD = 3.3 V, sampling rate = 125 MSPS, 50% clock duty cycle, 3-VPP differential clock, and CLOAD = 10 pF, unless
otherwise noted
=
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Switching Specification
tA
Aperture delay
Input CLK falling edge to data sampling point
Uncertainty in sampling instant
Data valid(3) to 50% of CLKOUT rising edge
1
300
2.7
2
ns
fs
Aperture jitter (uncertainty)
Data setup time
tSETUP
tHOLD
tSTART
tEND
2.3
1.7
ns
ns
50% of CLKOUT rising edge to data becoming
invalid(3)
Data hold time
Input clock to output data
Input clock rising edge to data valid start delay
Input clock rising edge to data valid end delay
2
2.6
ns
ns
(4)(5)
valid start
Input clock to output data
5.8
4.2
6.9
(4)(5)
valid end
tJIT
tr
Output clock jitter
Uncertainty in CLKOUT rising edge, peak-to-peak
Rise time of CLKOUT from 20% to 80% of DRVDD
Fall time of CLKOUT from 80% to 20% of DRVDD
150
1.7
1.5
4.8
210
1.9
1.7
5.5
psPP
ns
Output clock rise time
Output clock fall time
tf
ns
tPDI
Input clock to output clock
delay
Input clock rising edge, zero crossing, to output
clock rising edge 50%
ns
tr
tf
Data rise time
Data rise time measured from 20% to 80% of
DRVDD
3.6
2.8
4.6
3.7
ns
ns
Data fall time
Data fall time measured from 80% to 20% of
DRVDD
Output enable(OE) to data
output delay
Time required for outputs to have stable timings
with regard to input clock(6) after OE is activated
1000
1000
1000
Clock
cycles
Time to valid data after coming out of software
power down
Clock
cycles
Wakeup time
Latency
Time to valid data after stopping and restarting the
clock
Clock
cycles
Time for a sample to propagate to the ADC outputs
17.5
(1) Timing parameters are ensured by design and characterization, and not tested in production.
(2) See Table 5 through Table 8 in the Application Information section for timing information at additional sampling frequencies.
(3) Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW.
(4) See the Output Information section for details on using the input clock for data capture.
(5) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 2). Add 1/2 clock period for the valid
number for a falling edge CLKOUT polarity.
(6) Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect
to input clock.
6
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