ADS5510
www.ti.com
SLAS499–JANUARY 2007
RS
RG
RF
+5V
RT
+3.3V
m
m
10 F
0.1 F
RIN
RIN
INP
ADS5510
VOCM
11-Bit / 125MSPS
INM
m
1 F
THS4503
CM
m
m
10 F
0.1 F
W
10
-
5V
RG
RF
m
0.1 F
Figure 27. Using the THS4503 with the ADS5510
POWER-SUPPLY SEQUENCE
The preferred power-up sequence is to ramp AVDD first, followed by DRVDD, including a simultaneous ramp of
AVDD and DRVDD. In the event that DRVDD ramps up first in the system, care must be taken to ensure that AVDD
ramps up within 10 ms. Optionally, it is recommended to put a 2-kΩ resistor from REFP (pin 29) to AVDD as
shown in Figure 28. This helps to make the device more robust to power supply ramp-up timings.
28
AVDD
2 kW
29
REFP
1 W
1 mF
Figure 28.
POWER-DOWN
The device enters power-down in one of two ways: either by reducing the clock speed or by setting the PDN bit
throughout the serial programming interface. Using the reduced clock speed, power-down may be initiated for
clock frequency below 2 MSPS. The exact frequency at which the power down occurs varies from device to
device.
Using the serial interface PDN bit to power down the device places the outputs in a high-impedance state and
only the internal reference remains on to reduce the power-up time. The power-down mode reduces power
dissipation to approximately 180 mW.
21
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