+5V
+5V
1/2
OPA2234
REFT
4.7kΩ
+
2.2µF
0.1µF
R3
ADS5421
R4
R1
+
REF1004
+2.5V
10µF
1/2
OPA2234
REFB
+
R2
0.1µF
2.2µF
0.1µF
FIGURE 9. Example for an External Reference Circuit Using a Dual, Single-Supply Op Amp.
DIGITAL INPUTS AND OUTPUTS
CLOCK INPUT
CLK
ADS5421
TTL/CMOS
Clock Source
(3V/5V)
Unlike most ADCs, the ADS5421 contains internal clock
conditioning circuitry. This enables the converter to adapt to
a variety of application requirements and different clock
CLK
sources. With no input signal connected to either clock pin,
47nF
the threshold level is set to approximately +1.6V by the on-
chip resistive voltage divider, as shown in Figure 10. The
parallel combination of R1 || R2 and R3 || R4 sets the input
FIGURE 11. Single-Ended TTL/CMOS Clock Source.
impedance of the clock inputs (CLK, CLK) to approximately
2.7kΩ single-ended, or 5.5kΩ differentially. The associated
ground referenced input capacitance is approximately 5pF
for each input. If a logic voltage other than the nominal +1.6V
is desired, the clock inputs can be externally driven to
establish an alternate threshold voltage.
Applying a single-ended clock signal will provide satisfactory
results in many applications. However, unbalanced high-speed
logic signals can introduce a high amount of disturbances,
such as ringing or ground bouncing. In addition, a high
amplitude can cause the clock signal to have unsymmetrical
rise-and-fall times, potentially affecting the converter distortion
performance. Proper termination practice and a clean PC
board layout will help to keep those effects to a minimum.
+5V
ADS5421
To take full advantage of the excellent distortion performance
of the ADS5421, it is recommended to drive the clock inputs
differentially. A differential clock improves the digital
feedthrough immunity and minimizes the effect of modulation
between the signal and the clock. Figure 12 illustrates a
simple method of converting a square wave clock from
single-ended to differential using an RF transformer. Small
surface-mount transformers are readily available from sev-
eral manufacturers (e.g., model ADT1-1 by Mini-Circuits). A
capacitor in series with the primary side may be inserted to
block any DC voltage present in the signal. The secondary
side connects directly to the two clock inputs of the converter
because the clock inputs are self-biased.
R1
8.5kΩ
R3
8.5kΩ
CLK
CLK
R2
4kΩ
R4
4kΩ
FIGURE 10. The Differential Clock Inputs are Internally Biased.
The ADS5421 can be interfaced to standard TTL or CMOS
logic and accepts 3V or 5V compliant logic levels. In this
case, the clock signal should be applied to the CLK input,
whereas the complementary clock input (CLK) should be
bypassed to ground by a low-inductance ceramic chip ca-
pacitor, as shown in Figure 11. Depending on the quality of
the signal, inserting a series, damping resistor can be benefi-
cial to reduce ringing. When digitizing at high sampling rates
the clock should have a 50% duty cycle (tH = tL) to maintain
good distortion performance.
XFR
1:1
RS
0.1µF
Square Wave
or Sine Wave
Clock Source
CLK
ADS5421
RT
CLK
FIGURE 12. Connecting a Ground-Referenced Clock Source
to the ADS5421 Using an RF Transformer.
ADS5421
14
SBAS237D
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