The top and bottom reference outputs can be used to provide
up to 1mA of current (sink or source) to external circuits.
Degradation of the differential linearity (DNL) and, conse-
quently, the dynamic performance, of the ADS5421 may
occur if this limit is exceeded.
REFERENCE
REFERENCE OPERATION
Integrated into the ADS5421 is a bandgap reference circuit,
including logic that provides a +1V, +1.5V, or +2V reference
output by selecting the corresponding pin-strap configura-
tion. Table I lists a complete overview of the possible refer-
ence options and pin configurations.
USING EXTERNAL REFERENCES
For even more design flexibility, the ADS5421 can be oper-
ated with external references. The utilization of an external
reference voltage may be considered for applications requir-
ing higher accuracy, improved temperature stability, or a
continuous adjustment of the converter full-scale range.
Especially in multichannel applications, the use of a common
external reference offers the benefit of improving the gain
matching between converters. Selection between internal or
external reference operation is controlled through the VREF
pin. The internal reference will become disabled if the voltage
applied to the VREF pin exceeds +3.5VDC. Once selected, the
ADS5421 requires two reference voltages: a top reference
voltage applied to the REFT pin and a bottom reference
voltage applied to the REFB pin (see Table I). As illustrated
in Figure 9, a micropower reference (REF1004) and a dual,
single-supply amplifier (OPA2234) can be used to generate
a precision external reference. Note that the function of the
range select pins, SEL1 and SEL2, are disabled while the
converter is operating in external reference mode.
Figure 8 shows the basic model of the internal reference
circuit. The functional blocks are a 1V bandgap voltage
reference, a selectable gain amplifier, the drivers for the top
and bottom reference (REFT, REFB), and the resistive refer-
ence ladder. The ladder resistance measures approximately
1kΩ between the REFT and REFB pins. The ladder is split
into two equal segments establishing a common-mode volt-
age at the ladder midpoint, labeled CM. The ADS5421
requires solid bypassing for all reference pins to keep the
effects of clock feedthrough to a minimum and to achieve the
specified level of performance. Figure 8 shows the recom-
mended decoupling scheme. All 0.1µF capacitors must be
located as close to the pins as possible. In addition, pins
REFT, CM, and REFB must be decoupled with tantalum
surface-mount capacitors (2.2µF or 4.7µF).
When operating the ADS5421 with the internal reference, the
effective full-scale input span for each of the inputs, IN and
IN, is determined by the voltage at the VREF pin, given to:
(1)
Input Span (differential, each input) = VREF = (REFT – REFB) in Vp-p
DESIRED FULL-SCALE
RANGE (FSR)
(DIFFERENTIAL)
CONNECT
SEL1 (PIN 45) TO:
CONNECT
SEL2 (PIN 44) TO:
VOLTAGE AT VREF
(PIN 46)
VOLTAGE AT REFT
(PIN 52)
VOLTAGE AT REFB
(PIN 50)
4Vp-p (+16dBm)
3Vp-p (+13dBm)
2Vp-p (+10dBm)
External Reference
GND
GND
VREF
—
GND
+VSA
GND
—
+2.0V
+1.5V
+3.5V
+3.25V
+1.5V
+1.75V
+1.0V
+3.0V
+2.0V
> +3.5V
+2.75V to +4.5V
+0.5V to +2.25V
TABLE I. Reference Pin Configurations and Corresponding Voltages on the Reference Pins.
SEL1 SEL2
45
44
Range Select
and
Gain Amplifier
Top
Reference
Driver
REFBY
0.1µF
REFT
CM
+
+
+
52
500Ω
61
0.1µF
0.1µF
0.1µF
2.2µF
2.2µF
2.2µF
+1VDC
Bandgap
Reference
51
500Ω
Bottom
Reference
Driver
REFB
50
ADS5421
46
0.1µF
VREF
FIGURE 8. Internal Reference Circuit of the ADS5421 and Recommended Bypass Scheme.
ADS5421
SBAS237D
13
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