DIGITAL INPUTS AND OUTPUTS
SINGLE-ENDED INPUT
IN = CM, Pins 52, 61)
STRAIGHT OFFSET BINARY
(SOB)
(
Clock Input Requirements
+FS–1LSB (IN = CMV + FSR/2)
1111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0000
Both channels of the ADS2806 are controlled by the same
clock on the rising edge. Utilizing a single clock reduces
timing uncertainty in the sampling of the two channels.
Clock jitter is critical to the SNR performance of high-speed,
high-resolution ADCs. Clock jitter leads to aperture jitter (tA),
which adds noise to the signal being converted. The
ADS2806 samples the input signal on the rising edge of the
CLK input. Therefore, this edge should have the lowest
possible jitter. The jitter noise contribution to total SNR is
given by the following equation. If this value is near your
system requirements, input clock jitter must be reduced.
+1/2 FS
Bipolar Zero (IN = VCM
)
–1/2 FS
–FS (IN = CMV – FSR/2)
TABLE II. Coding Table for Single-Ended Input Configuration
with IN Tied to the Common-Mode Voltage.
STRAIGHT OFFSET BINARY
DIFFERENTIAL INPUT
(SOB)
+FS–1LSB (IN = +3V, IN = +2V)
1111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0000
+1/2 FS
1
Jitter SNR = 20log
rms signal to rms noise
Bipolar Zero (IN = IN = VCM
)
2πƒIN tA
–1/2 FS
where: ƒIN is input signal frequency
–FS (IN = +2V, IN = +3V)
tA is rms clock jitter
TABLE III. Coding Table for Differential Input Configuration.
Particularly in undersampling applications, special consider-
ation should be given to clock jitter. The clock input should be
treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should have
50% duty cycle (tH = tL), along with fast rise and fall times of
2ns or less. The clock input of the ADS2806 can be driven
with either 3V or 5V logic levels. Using low-voltage logic (3V)
may lead to improved AC performance of the converter.
Data output is in the form of two parallel words. It is
recommended that the capacitive loading on the data lines
be as low as possible (< 15pF). Higher capacitive loading
will cause larger dynamic currents as the digital outputs are
changing. Those high current surges can feed back to the
analog portion of the ADS2806 and affect the performance.
If necessary, external buffers or latches close to the
converter’s output pins may be used to minimize the capaci-
tive loading. They also provide the added benefit of isolating
the ADS2806 from high-frequency digital noise on the bus
coupling back into the converter.
Over Range Indicator (OVR)
If the analog input voltage exceeds the set full-scale range,
an over range condition exists. The “OVR” pin of the ADS2806
can be used to monitor any such out-of-range condition. This
“OVR” output is updated along with the data output corre-
sponding to the particular sampled analog input voltage.
Therefore, the OVR data is subject to the same pipeline
delay as the digital data. The OVR output is LOW when the
input voltage is within the defined input range. It will go HIGH
if the applied signal exceeds the full-scale range.
Digital Output Driver Supply (VDRV)
Each channel of the ADS2806 has a separate dedicated
supply pin (8, 40) for the output logic drivers, VDRV, which
are not internally connected to the other supply pins. Setting
the voltage at VDRV to +5V or +3V, the ADS2806 produces
corresponding logic levels and can directly interface to the
selected logic family. The output stages are designed to
supply sufficient current to drive a variety of logic families.
However, it is recommended to use the ADS2806 with +3V
logic supply. This will lower the power dissipation in the
output stages due to the lower output swing and reduce
current glitches on the supply line that may affect the AC
performance of the converter. In some applications, it might
be advantageous to decouple the VDRV pin with additional
capacitors or a pi-filter.
Data Outputs
The digital outputs of the ADS2806 can be set to a high-
impedance state by driving OE (pins 6 and 42) with a logic
HIGH. Normal operation is achieved with pins 6 and 42
LOW due to internal pull-down resistors. This function is
provided for testability purposes and is not meant to drive
digital buses directly, or be dynamically changed during the
conversion process. The output data format of the ADS2806
is in positive Straight Offset Binary code, as shown in
Tables II and III. This format can easily be converted into the
Binary Two’s Complement code by inverting the MSB.
OUTPUT ENABLE (OE
)
The digital outputs of the ADS2806 can be set to high
impedance (tri-state) by driving OEA and OEB (pins 6, 42)
with a logic HIGH. Normal operation is achieved with the
same pins pulled LOW.
ADS2806
SBAS178B
15
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