ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
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SBAS274E − MARCH 2003 − REVISED JUNE 2004
CLK
t11
t9
RESET
t26
t25
DRDY
t23
t24
R
D
Figure 6. Reset Timing (ADS1606 with FIFO Enabled)
TIMING REQUIREMENTS FOR FIGURE 6
SYMBOL
DESCRIPTION
MIN
50
TYP
MAX
UNIT
ns
t
9
RESET pulse width
t
11
−5
10
ns
RESET rising edge to falling edge of CLK
CLK
Cycles
t
8
8
RD pulse low after RESET goes high
23
CLK
Cycles
t
24
RD pulse high before first DRDY pulse after RESET goes high
DRDY low after RESET goes low
CLK
Cycles
t
25
8 × (FIFO level + 1)
DRDY
Cycles
See Table 4
t
26
Delay from RESET high to valid DOUT (settling to 0.001%)
11
BB [ BURR-BROWN CORPORATION ]
