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ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
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SBAS274E − MARCH 2003 − REVISED JUNE 2004
t1
t2
CLK
t2
t13
t14
DRDY
t15
t16
CS(1
)
t21
t17
t20
R
D
t18
t19
DOUT[15:0]
D1
D2
DL(2)
(1) CS may be tied low.
(2) The number of data readings (DL) is set by the FIFO level.
Figure 4. Data Retrieval Timing (ADS1606 with FIFO Enabled)
RD, CS
t7
t8
DOUT[15:0]
Figure 5. DOUT Inactive/Active Timing (ADS1606 with FIFO Enabled)
TIMING REQUIREMENTS FOR FIGURE 4 AND FIGURE 5
SYMBOL
DESCRIPTION
MIN
20
TYP
MAX
UNIT
t
1
25
1000
ns
ns
ns
CLK period (1/f
)
CLK
t
2
10
CLK pulse width, high or low
t
7
7
7
15
15
Rising edge of RD and/or CS inactive (high) to DOUT high impedance
t
8
ns
ns
Falling edge of RD and/or CS active (low) to DOUT active.
Rising edge of CLK to DRDY high
t
13
12
CLK
Cycles
(1)
t
14
8 × FIFO Level
DRDY period
CLK
Cycles
t
15
1
DRDY positive pulse width
t
0
0
ns
ns
ns
ns
RD high hold time after DRDY goes low
CS low before RD goes low
RD negative pulse width
16
t
17
t
18
10
10
t
19
t
20
t
21
RD positive pulse width
CLK
Cycles
2
0
RD high before DRDY toggles
RD high before CS goes high
ns
NOTE: DOUT[15:0] and DRDY load = 10pF.
(1)
See FIFO section for more details.
10
BB [ BURR-BROWN CORPORATION ]
