ADS1274
ADS1278
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SBAS367–JUNE 2007
1
2
22
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
23
24
25
26
SCLK
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
ADS1278 Only
DRDY
(SPI)
FSYNC
(Frame-Sync)
Figure 80. Discrete Data Output Mode
Table 13. Maximum Channels in a Daisy-Chain
DAISY-CHAINING
(fSCLK = fCLK
)
Multiple ADS1274/78s can be daisy-chained together
to output data on a single pin. The DOUT1 data
output pin of one device is connected to the DIN of
the next device. As shown in Figure 81, the DOUT1
pin of device 1 provides the output data to a
controller, and the DIN of device 2 is grounded.
Figure 82 shows the data format when reading back
data.
MAXIMUM NUMBER
OF CHANNELS
MODE SELECTION
High-Speed
CLKDIV
1
1
1
0
1
0
10
21
High-Resolution
21
Low-Power
Low-Speed
10
106
21
The maximum number of channels that may be
daisy-chained in this way is limited by the frequency
of fSCLK, the mode selection, and the CLKDIV input.
The frequency of fSCLK must be high enough to
completely shift the data out from all channels within
one fDATA period. Table 13 lists the maximum number
Whether the interface protocol is SPI or Frame-Sync,
it is recommended to synchronize all devices by tying
the SYNC inputs together. When synchronized in SPI
protocol, it is only necessary to monitor the DRDY
output of one ADS1274/78.
of daisy-chained channels when fSCLK = fCLK
.
To increase the number of data channels possible in
a chain, a segmented DOUT scheme may be used,
producing two data streams. Figure 83 illustrates four
In Frame-Sync interface protocol, the data from all
devices are ready after the rising edge of FSYNC.
Since DOUT1 and DIN are both shifted on the falling
edge of SCLK, the propagation delay on DOUT1
creates a setup time on DIN. Minimize the skew in
SCLK to avoid timing violations.
ADS1274/78s,
with
pairs
of
ADS1274/78s
daisy-chained together. The channel data of each
daisy-chained pair are shifted out in parallel and
received by the processor through independent data
channels.
33
Copyright © 2007, Texas Instruments Incorporated
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