ADS1274
ADS1278
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SBAS367–JUNE 2007
DOUT
FRAME-SYNC SERIAL INTERFACE
The conversion data are shifted out on
DOUT[4:1]/[8:1]. The MSB data become valid on
DOUT[4:1]/[8:1] after FSYNC goes high. The
subsequent bits are shifted out with each falling edge
of SCLK. If daisy-chaining, the data shifted in using
DIN appear on DOUT[4:1]/[8:1] after all channel data
have been shifted out. When the device is configured
for modulator output, DOUT becomes the modulator
data output (see the Modulator Output section).
Frame-Sync format is similar to the interface often
used on audio ADCs. It operates in slave
fashion—the user must supply framing signal FSYNC
(similar to the left/right clock on stereo audio ADCs)
and the serial clock SCLK (similar to the bit clock on
audio ADCs). The data are output MSB first or
left-justified on the rising edge of FSYNC. When
using Frame-Sync format, the FSYNC and SCLK
inputs must be continuously running with the
relationships shown in the Frame-Sync Timing
Requirements.
DIN
This input is used when multiple ADS1274/78s are to
be daisy-chained together. It can be used with either
SPI or Frame-Sync formats. Data are shifted in on
the falling edge of SCLK. When using only one
ADS1274/78, tie DIN low. See the Daisy-Chaining
section for more information.
SCLK
The serial clock (SCLK) features a Schmitt-triggered
input and shifts out data on DOUT on the falling
edge. It also shifts in data on the falling edge on DIN
when this pin is being used for daisy-chaining. Even
though SCLK has hysteresis, it is recommended to
keep SCLK as clean as possible to prevent glitches
from accidentally shifting the data. When using
Frame-Sync format, SCLK must run continuously. If it
is shut down, the data readback will be corrupted.
The number of SCLKs within a frame period (FSYNC
clock) can be any power-of-2 ratio of CLK cycles (1,
1/2, 1/4, etc), as long as the number of cycles is
sufficient to shift the data output from all channels
within one frame. When the device is configured for
modulator output, SCLK becomes the modulator
clock output (see the Modulator Output section).
DOUT MODES
For both SPI and Frame-Sync interface protocols, the
data are shifted out either through individual channel
DOUT pins, in a parallel data format (Discrete mode),
or the data for all channels are shifted out, in a serial
format, through a common pin, DOUT1 (TDM mode).
TDM Mode
In TDM (time-division multiplexed) data output mode,
the data for all channels are shifted out, in sequence,
on a single pin (DOUT1). As shown in Figure 77, the
data from channel 1 are shifted out first, followed by
channel 2 data, etc. After the data from the last
channel are shifted out, the data from the DIN input
follow. The DIN is used to daisy-chain the data output
from an additional ADS1274/78 or other compatible
device. Note that when all channels of the
ADS1274/78 are disabled, the interface is disabled,
rendering the DIN input disabled as well. When one
or more channels of the device are powered down,
the data format of the TDM mode can be fixed or
dynamic.
DRDY/FSYNC (Frame-Sync Format)
In Frame-Sync format, this pin is used as the FSYNC
input. The frame-sync input (FSYNC) sets the frame
period, which must be the same as the data rate. The
required number of fCLK cycles to each FSYNC period
depends on the mode selection and the CLKDIV
input. Table 6 indicates the number of CLK cycles to
each frame (fCLK/fDATA). If the FSYNC period is not
the proper value, data readback will be corrupted.
SCLK
1
2
23
24
25
47
48
49
71
CH3
CH3
73
95
96
97
167
168
169
191
192
193
194
195
72
DOUT1
(ADS1274)
CH1
CH1
CH2
CH4
DIN
CH5
DOUT1
(ADS1278)
CH2
CH4
CH7
CH8
DIN
DRDY
(SPI)
FSYNC
(Frame-Sync)
Figure 77. TDM Mode (All Channels Enabled)
31
Copyright © 2007, Texas Instruments Incorporated
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