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ADS1274IPAPRG4 参数 Datasheet PDF下载

ADS1274IPAPRG4图片预览
型号: ADS1274IPAPRG4
PDF下载: 下载PDF文件 查看货源
内容描述: 四/八通道,同步采样, 24位模拟至数字转换器 [Quad/Octal, Simultaneous Sampling, 24-Bit Analog-to-Digital Converters]
分类和应用: 转换器
文件页数/大小: 49 页 / 1821 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ADS1274  
ADS1278  
www.ti.com  
SBAS367JUNE 2007  
OVERVIEW  
High-Speed, High-Resolution, Low-Power, and  
Low-Speed. Table 1 summarizes the performance of  
each mode.  
The ADS1274 (quad) and ADS1278 (octal) are 24-bit,  
delta-sigma ADCs based on the single-channel  
ADS1271. They offer the combination of outstanding  
dc accuracy and superior ac performance. Figure 57  
shows the block diagram. Note that both devices are  
functionally the same, except that the ADS1274 has  
four ADCs and the ADS1278 has eight ADCs. The  
packages are identical, and the ADS1274 pinout is  
compatible with the ADS1278, permitting true drop-in  
expandability. The converters are comprised of four  
(ADS1274) or eight (ADS1278) advanced, 6th-order,  
chopper-stabilized, delta-sigma modulators followed  
by low-ripple, linear phase FIR filters. The modulators  
measure the differential input signal, VIN = (AINP –  
In High-Speed mode, the maximum data rate is  
128kSPS (when operating at 128kSPS, Frame-Sync  
format must be used). In High-Resolution mode, the  
SNR = 111dB (VREF = 3.0V); in Low-Power mode, the  
power dissipation is 31mW/channel; and in  
Low-Speed mode, the power dissipation is only  
7mW/channel at 10.5kSPS. The digital filters can be  
bypassed, enabling direct access to the modulator  
output.  
The ADS1274/78 is configured by simply setting the  
appropriate I/O pins—there are no registers to  
program. Data are retrieved over a serial interface  
that supports both SPI and Frame-Sync formats. The  
ADS1274/78 has a daisy-chainable output and the  
ability to synchronize externally, so it can be used  
conveniently in systems requiring more than eight  
channels.  
AINN), against the differential reference, VREF  
=
(VREFP – VREFN). The digital filters receive the  
modulator signal and provide a low-noise digital  
output. To allow tradeoffs among speed, resolution,  
and power, four operating modes are supported:  
VREFP  
AVDD  
VREFN  
DVDD  
IOVDD  
Mod 1  
Mod 2  
R
S
Modulator  
Output  
VCOM  
VREF  
R
Mod 8  
VIN1  
DS  
AINP1  
AINN1  
Digital  
DRDY/FSYNC  
SCLK  
S
S
Modulator1  
SPI  
and  
Filter1  
DOUT[4:1]/[8:1](1)  
Frame-Sync  
Interface  
DIN  
VIN2  
DS  
AINP2  
AINN2  
Digital  
Filter2  
Modulator2  
TEST[1:0]  
FORMAT[2:0]  
CLK  
Control  
Logic  
SYNC  
PWDN[4:1]/[8:1](1)  
AINP4/8(1)  
AINN4/8(1)  
VIN4/8  
DS  
Modulator4/8(1)  
Digital  
Filter4/8(1)  
CLKDIV  
S
MODE[1:0]  
AGND  
DGND  
NOTE: (1) The ADS1274 has four channels; the ADS1278 has eight channels.  
Figure 57. ADS1274/ADS1278 Block Diagram  
Table 1. Operating Mode Performance Summary  
MODE  
High-Speed  
High-Resolution  
Low-Power  
Low-Speed  
MAX DATA RATE (SPS)  
PASSBAND (kHz)  
57,984  
SNR (dB)  
106  
NOISE(μVRMS  
)
POWER/CHANNEL (mW)  
128,000  
52,734  
52,734  
10,547  
8.5  
5.5  
8.5  
8.0  
70  
64  
31  
7
23,889  
110  
23,889  
106  
4,798  
107  
20  
Copyright © 2007, Texas Instruments Incorporated  
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Product Folder Link(s): ADS1274 ADS1278  
 
 
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