Normal
Mode
Normal
Mode
Self-Calibration
Mode
Offset
Calibration on
Internal Offset(2)
Full-Scale
Calibration on
Internal Full-Scale
Analog
Input
Conversion
Valid
Data
Valid
Data
Valid
Data
Valid
Data
DRDY
SC(1)
Serial
I/O
tDATA
NOTES: (1) SC = Self-Calibration instruction. (2) In Slave Mode, this function requires 4 cycles.
FIGURE 5. Self-Calibration Timing.
Mode bits are reset to 000 (Normal Mode). A single conver-
sion is done with DRDY HIGH. After this conversion, the
DRDY signal goes LOW indicating resumption of normal
operation.
Self-Calibration
A self-calibration is performed after the bits 001 have been
written to the Command Register Operation Mode bits
(MD2 through MD0). This initiates the following sequence
at the start of the next conversion cycle (see Figure 5). The
DRDY signal will not go LOW but will remain HIGH and
will continue to remain HIGH throughout the calibration
sequence. The inputs to the sampling capacitor are discon-
nected from the converter’s analog inputs and are shorted
together. An offset calibration is performed over the next
three conversion periods (four in Slave Mode). Then, the
input to the sampling capacitor is connected across REFIN,
and a full-scale calibration is performed over the next three
conversions.
Normal operation returns within a single conversion cycle
because it is assumed that the input voltage at the converter’s
input is not removed immediately after the offset calibration
is performed. In this case, the digital filter already contains
a valid result.
For full system calibration, offset calibration must be per-
formed first and then full-scale calibration. In addition, the
offset calibration error will be the rms sum of the conversion
error and the noise on the system offset voltage. See the
System Calibration Limits section for information regarding
the limits on the magnitude of the system offset voltage.
After this, the Operation Mode bits are reset to 000 (Normal
Mode) and the input capacitor is reconnected to the input.
Conversions proceed as usual over the next three cycles in
order to fill the digital filter. DRDY remains HIGH during
this time. On the start of the fourth cycle , DRDY goes LOW
indicating valid data and resumption of normal operation.
System Full-Scale Calibration
A system full-scale calibration is performed after the bits
011 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 7). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The full-scale calibration will be per-
formed on the differential input voltage (2 • REFIN/G)
present at the converter’s input over the next three conver-
sion periods (four in Slave Mode). When this is done, the
Operation Mode bits are reset to 000 (Normal Mode). A
single conversion is done with DRDY HIGH. After this
conversion, the DRDY signal goes LOW indicating resump-
tion of normal operation.
System Offset Calibration
A system offset calibration is performed after the bits 010
have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 6). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The offset calibration will be per-
formed on the differential input voltage present at the
converter’s input over the next three conversion periods
(four in Slave Mode). When this is done, the Operation
Normal
Mode
System Full-Scale
Calibration Mode
Normal
Mode
Normal
Mode
System Offset
Calibration Mode
Normal
Mode
Full-Scale
Calibration on
System Full-Scale(2)
Analog
Input
Conversion
Possibly Possibly
Valid
Data
Offset
Calibration on
System Offset(2)
Analog
Input
Conversion
Possibly Possibly
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
DRDY
DRDY
SFSC(1)
SOC(1)
Serial
I/O
Serial
I/O
tDATA
tDATA
NOTES: (1) SFSC = System Full-Scale Calibration instruction.
(2) In Slave Mode, this function requires 4 cycles.
NOTES: (1) SOC = System Offset Calibration instruction.
(2) In Slave Mode, this function requires 4 cycles.
FIGURE 7. System Full-Scale Calibration Timing.
FIGURE 6. System Offset Calibration Timing.
ADS1212, 1213
14
SBAS064A
BB [ BURR-BROWN CORPORATION ]
