Because the last data-word is stored in the data latch, it is
possible to read it during the next A/D conversion. Assertion
of CS and HBEN for reading parallel data should be timed
from Status going low. The two-byte read operation must be
complete before the conversion in process is complete or the
Data Read is invalid.
Analog
In
SHC76
ADC700
Mode
Control
Serial Data is available during continuous conversion with
word synchronization available from STATUS.
Sample
Mode
Control
Hold
USING A SAMPLE/HOLD WITH ADC700
1µs to 3µs
Figure 12 illustrates using ADC700 with the Burr-Brown
SHC76. The sample-to-hold settling time (to 14 bits,
±0.003%FSR) of the SHC76 is 1µs typ, 3µs max. The time
from the Status going High to the first conversion decision
is about 900ns. Therefore a time delay between the Sample-
to-Hold command to the WR command to the ADC700 is
required.
ADC700
WR
Start Conversion
FIGURE 12. Using Sample/Hold with ADC700 Requires
TimeDelayBetweenSampleandStart-of-Con-
version.
®
ADC700
12
BB [ BURR-BROWN CORPORATION ]
