ADC700
CS
Serial
Data
WR
VDD
VDD
To Interrupt
ADC700
Status
Serial
Data
FIGURE 11. Continuous Conversion Circuit Connection.
Strobe
Reset
Isolation Barrier
FIGURE 10. Serial Data Output Providing Convenient
Isolation.
PIN DESIGNATION
DEFINITION
FUNCTION
CS (Pin 9)
Chip Select
Write (Convert)
Read
High Byte Enable
“1” = Low Byte
“0” = High Byte
Reset
Must be Low to either initiate a conversion or read output data.
WR (Pin 7)
RD (Pin 8)
HBEN (Pin 10)
Conversion begins after the High-to-Low transition.
Turns ON the three-state output drivers upon being asserted low.
Selects the MSB or the LSB for readout. Data Ready is cleared when HBEN is Low and RD is asserted.
Reset (Pin 6)
Resets internal logic. Must be asserted after power-up or a power interruption clears Status and Data
Ready to Low.
BTCEN (Pin 23)
BTC Enable
Sets the output code to Binary Twos Complement (BTC) when Low. Output code is Bipolar Offset Binary
(BOB) when High.
TABLE III. Control Line Functions.
CONTROL LINE
RESET
WR
RD
HBEN
CS
OPERATION
0
1
1
1
1
1
1
X
X
0
1
1
0
0
X
X
X
0
0
0
0
X
X
X
0
1
0
1
X
1
0
0
0
0
0
Reset converter logic. Status and Data Ready set Low.
No operation.
Initiate conversion.
Places High Byte on output port. Clears Data Ready flag.
Placed Low Byte on output port. Does not clear Data Ready flag.
Initiates conversion and places High Byte or output port. Clears Data Ready.
Initiates conversion and places Low Byte on output port. Does not clear Data Ready flag.
NOTE: If a conversion command is asserted while a conversion is in progress, the command is ignored. If the conversion command remains asserted when a
conversion is finished, a new conversion will begin.
TABLE IV. Control Input Truth Table.
®
11
ADC700
BB [ BURR-BROWN CORPORATION ]
