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ADC601SG 参数 Datasheet PDF下载

ADC601SG图片预览
型号: ADC601SG
PDF下载: 下载PDF文件 查看货源
内容描述: [A/D Converter, 12-Bit, 1 Func, Hybrid, CDIP32,]
分类和应用: 转换器
文件页数/大小: 4 页 / 43 K
品牌: BB [ BURR-BROWN CORPORATION ]
 浏览型号ADC601SG的Datasheet PDF文件第1页浏览型号ADC601SG的Datasheet PDF文件第3页浏览型号ADC601SG的Datasheet PDF文件第4页  
SPECIFICATIONS  
ELECTRICAL  
TCASE = +25°C, 900ns conversion time, ±VCC = ±15V, +VDD = +5V, and 6-minute warm-up in a normal convection environment unless otherwise noted.  
ADC601JG  
TYP  
ADC601KG  
TYP  
PARAMETER  
CONDITIONS  
MIN  
MAX  
MIN  
MAX  
UNITS  
RESOLUTION  
12  
*
Bits  
ANALOG CHARACTERISTICS  
INPUTS  
Voltage Ranges: Bipolar  
Unipolar  
Full Scale(FSR)(1)(2)  
Full Scale(FSR)(1)(2)  
±5, ±10  
0 to –10  
1.4  
*
*
*
*
V
V
kΩ  
kΩ  
Impedance:  
–10V to 0V, ±5V  
±10V  
2.4  
TRANSFER CHARACTERISTICS  
ACCURACY  
Gain Error(3)  
990ns Conversion Time  
990ns Conversion Time  
990ns Conversion Time  
990ns Conversion Time  
990ns Conversion Time  
±0.08  
±0.12  
±0.08  
±0.55  
±1.2  
±0.8  
±0.024  
±0.024  
*
*
*
±0.2  
±0.5  
±0.25  
±0.012  
±0.012  
%
Input Offset Error(3): Unipolar  
Bipolar  
% of FSR  
% of FSR  
% of FSR  
% of FSR  
Integral Linearity Error  
Differential Linearity Error  
No Missing Codes  
Guaranteed  
Power Supply Rejection of Offset and Gain  
+VCC = ±5%  
–VCC = ±5%  
+VDD = ±5%  
±0.0036  
±0.0005  
±0.001  
*
*
%FSR/%VCC  
%FSR/%VCC  
%FSR/%VDD  
*
DIGITAL CHARACTERISTICS  
INPUT  
Logic Family  
TTL-Compatible CMOS  
Convert Command Logic Voltages  
Logic Low  
Logic High  
Logic Low  
Logic High  
0
+2  
+0.8  
+VDD  
–150  
–150  
*
*
*
*
V
V
µA  
µA  
Convert Command Currents  
Convert Command  
High Level When Converting  
CONVERSION TIME  
Factory Set  
Power Supply Rejection of Conversion Time  
Without User Adjustment  
0.9  
±1  
1
*
*
*
µs  
ns/%VDD  
D +VDD = ±5%  
OUTPUT  
Logic Family  
Bits 1 through 12, Serial, Status, Clock Out  
TTL-Compatible CMOS  
+0.1 +0.4  
Logic Low, IOL = 3.2mA  
Logic High, IOH = –1mA  
*
*
*
*
*
V
V
MHz  
+2.7  
+4.9  
13  
*
Internal Clock Frequency  
Status  
Low Level When Data Valid  
DYNAMIC CHARACTERISTICS (4) (5) (6) Tested using Sample/Hold Amplifier SHC804 and ADC601 (See Typical Performance Curves)  
Differential Linearity Error  
Total Harmonic Distortion  
f
C = 10kHz: 68.3% of All Codes  
0.5  
0.8  
1.0  
0.4  
0.6  
0.7  
LSB  
LSB  
LSB  
99.7% of All Codes  
100% of All Codes  
fC = 10kHz, fS = 500kHz  
fC = 10kHz, fS = 1MHz  
fC = 250kHz, fS = 500kHz  
fC = 500kHz, fS = 1MHz  
–70  
–74  
–70  
–68  
*
*
*
*
dBc  
dBc  
dBc  
dBc  
Two-Tone Intermodulation Distortion(7)  
fC = 11kHz and 15kHz, fS = 500kHz  
–79  
–78  
–77  
*
*
*
dBc  
dBc  
dBc  
fC = 50kHz and 55kHz, fS = 500kHz  
C = 90kHz and 110kHz, fS = 500kHz  
f
Signal-to-Noise and Distortion  
(SINAD) Ratio  
fC = 250kHz, fS = 500kHz  
66  
65  
*
*
dB  
dB  
f
C = 500kHz, fS = 1MHz  
fC = 250kHz, fS = 500kHz  
C = 500kHz, fS = 1MHz  
Signal-to-Noise Ratio (SNR)  
68  
67  
*
*
dB  
dB  
f
PERFORMANCE OVER TEMPERATURE  
Gain  
T
T
T
MIN to TMAX  
MIN to TMAX  
MIN to TMAX  
±10  
±2  
±3  
±0.02  
±0.02  
±30  
±7  
±10  
*
*
*
*
*
*
ppm of FSR/°C  
ppm of FSR/°C  
ppm of FSR/°C  
% of FSR  
Input Offset:Unipolar  
Bipolar  
Internal Linearity Error  
Differential Linearity Error  
No Missing Codes  
Conversion Drift  
0.9µs Conversion Time TMIN to TMAX  
0.9µs Conversion Time TMIN to TMAX  
0.9µs Conversion Time TMIN to TMAX`  
±0.015  
±0.015  
% of FSR  
Guaranteed  
2
*
ns/°C  
®
ADC601  
2