AL462 4K2K Ultra HD FIFO Datasheet
8 TIMING DIAGRAM
Note: Signals in timing diagram denote the general symbols. In 32-bit data mode, 32-bit data are
synchronous with control signals denote “0” accordingly (WCLK0, WE0, RCLK0 and RE0 etc.).
In 16-bit x2 data mode, data bit 0 – 15 are synchronous with control signals denote “0” (WCLK0, WE0,
RCLK0 and RE0 etc.) while data bit 16 - 31 are synchronous with control signals denote “1” (WCLK1, WE1,
RCLK1 and RE1 etc.) accordingly.
PLRTY = VDD Timing
Reset
cycle (s)
cycle n
cycle 0
cycle 1
WCLK
WRST
DI31~0
TTR
TWRS
TWRH
TDS
TDH
n-1
n
0
1
/PLRTY=VDD , WEN= "L"
, IE= "L"
Write Cycle Timing (Write Reset)
cycle n
cycle n+1
Disable cycle (s)
cycle n+2
TWPL
WCLK
WEN
TWPH
TWC
TWES
TWEH
TWPW
TDS
TDH
DI31~0
DI15~0
n-1
n
n+1
n+2
/PLRTY=VDD ,IE="L" ,WRST="H"
Write Cycle Timing (Write Enable)
©2016~2019 by AverLogic Technologies, Corp.
18/38
AVERLOGIC [ AVERLOGIC TECHNOLOGIES INC ]
