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HFBR-782BHZ 参数 Datasheet PDF下载

HFBR-782BHZ图片预览
型号: HFBR-782BHZ
PDF下载: 下载PDF文件 查看货源
内容描述: 可插拔并行光纤模块,发射器和接收器 [Pluggable Parallel Fiber Optic Modules, Transmitter and Receiver]
分类和应用: 光纤放大器
文件页数/大小: 24 页 / 437 K
品牌: AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
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Receiver Electrical Characteristics  
(T = 0 °C to +80 °C, V = 3.3 V 5%, Typical T = +40 °C, V = 3.3 V)  
C
CC  
C
CC  
Parameter  
Symbol Min.  
Typ.  
Max.  
Unit  
Reference  
(Conditions)  
Supply Current  
ICCR  
400  
1.3  
445  
1.55  
120  
750  
mA  
W
1, Fig. 5  
Power Dissipation  
PDISR  
W
Differential Output Impedance  
ZOUT  
80  
100  
600  
2, Fig. 8, 10  
3, Figs. 7, 8  
DVDOUTP-P  
Data Output Differential Peak-to-Peak  
Voltage Swing  
450  
mVP-P  
Inter-channel Skew  
100  
110  
150  
150  
ps  
ps  
4
5
Differential Data Output Rise/Fall Time  
tr/tf  
Signal Detect Assert Time (OFF-to-ON)  
De-assert Time (ON-to-OFF)  
tSDA  
tSDD  
170  
190  
µs  
µs  
6
7
Control I/O  
LVTTL & LVCMOS Output Voltage High  
Compatible  
Output Voltage Low  
VOL  
VOH  
VEE  
2.5  
0.4  
VCC  
V
V
(IOL = 4.0 mA)  
(IOH = -0.5 mA)  
3.1  
Notes:  
1.  
I R is the dc supply current, dependent upon the number of active channels, where the Data Outputs are ac coupled with capacitors between the  
CC  
outputs and any resistive terminations. See Figure 7 for recommended termination.  
2. Measured over the range 4 MHz to 2 GHz.  
3. DV = DV – DV , where DV  
= High State Differential Data Output Voltage and DV = Low State Differential Data Output  
DOUTL  
, measured with a 100 W differential load connected with the recommended coupling capacitors  
DOUTP-P  
Voltage. DV  
DOUTH  
DOUTL  
DOUTH  
and DV  
= V  
– V  
DOUTH  
DOUTL  
DOUT+  
DOUT–  
and with a 2500 MBd, 8B10B serial encoded data pattern.  
4. Inter-channel Skew is defined for the condition of equal amplitude, zero ps skew input signals. Input power at –10 dBm.  
5. Rise and Fall Times are measured between the 20% and 80% levels using a 500 MHz square wave signal.  
6. The Signal Detect output will change from logic “0” (Low) to “1” (High) within the specified assert time for a step transition in optical input power  
from the de-asserted condition to the specified asserted optical power level on all 12 channels.  
7. The Signal Detect output will change from logic “1” (High) to “0” (Low) within the specified de-assert time for a step transition in optical input power  
from the specified asserted optical power level to the de-asserted condition on any 1 channel.  
7
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