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ACPM-7886 参数 Datasheet PDF下载

ACPM-7886图片预览
型号: ACPM-7886
PDF下载: 下载PDF文件 查看货源
内容描述: TD- SCDMA电源放大器器 [TD-SCDMA Power Amplifier]
分类和应用: 放大器
文件页数/大小: 14 页 / 355 K
品牌: AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
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iii. Ramp 2  
2.1  
The time in this zone should be kept below 35 seconds  
to reduce the risk of flux exhaustion. The ramp up rate  
should be 2°C/sec from 150°C to re-flow at 217°C. It is  
important that the flux medium retains its activity  
during this phase to ensure the complete coalescence  
of the solder particles during re-flow.  
0.375  
iv. Reflow  
The peak reflow temperature is calculated by adding  
~32°C to the melting point of the alloy. Lead free solder  
paste melts at 218°C and peak reflow temperature is  
218°C + 32°C = 250°C ( 5°C). Note that total time over  
218°C is critical and should typically be 60 – 150  
seconds. This period determines the appearance of the  
solder joints. Excessive time above reflow may cause a  
dull finish and charred of flux residues. Insufficient  
time above reflow may lead to poor wetting and  
improperly fused (cloudy) flux residues.  
0.375  
0.55  
Figure 3. PCB land pattern (dimensions in mm)  
1.68  
0.64  
v. Cooling  
Maximum slope for cooling is limited to 3°C/sec. More  
rapid cooling may cause solder joints crack while  
cooling at a slower rate will increase the likelihood of  
a crystalline appearance on the solder joints (dull  
finish).  
PCB Design Guidelines  
The recommended ACPM-7886 PCB land pattern is  
shown in Figure 3. The substrate is coated with solder  
mask between the I/O and conductive paddle to  
protect the gold pads from short circuit that is caused  
by solder bleeding / bridging.  
0.44  
0.64  
Figure 4. Stencil outline drawing (dimensions in mm)  
2.1  
0.55  
1.68  
Stencil Design Guidelines  
A properly designed solder screen or stencil is required  
to ensure optimum amount of solder paste is deposited  
onto the PCB pads. The recommended stencil layout is  
shown in Figure 4. The stencil has a solder paste  
deposition opening that is approximately 80% of the  
PCB pad. Reducing the stencil opening can potentially  
generate more voids. On the other hand, stencil  
openings larger than 100% will lead to excessive solder  
paste smear or bridging across the I/O pads or  
conductive paddle to adjacent I/O pads. Considering  
the fact that solder paste thickness will directly affect  
the quality of the solder joint, a good choice is to use  
laser cut stencil composed of 0.100mm (4 mils) or  
0.127mm (5 mils) thick stainless steel which is capable  
of producing the required fine stencil outline. The  
combined PCB and stencil layout is shown in Figure 5.  
Stencil  
Opening  
0.44  
Figure 5. Combined PCB and stencil layouts (dimensions in mm)  
9
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