FLASH
AS8F128K32
Austin Semiconductor, Inc.
FIGURE 13: Alternate CEx\ Controlled Write Operation Timings
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
NOTES:
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7\ = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
PARAMETER
COMMENTS
1
2
UNIT
TYP
1.0
14
MAX
4
Chip/Sector Erase Time
Byte Programming Time
15
sec
µs
Excludes 00h programming prior to erasure
Excludes system-level overhead5
1000
12.5
3
1.8
sec
Chip Programming Time
NOTES:
1. Typical program and erase times assume the following conditions: 25° C, 5.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V = 4.5 V (4.75 V for -45, -55 PDIP), 100,000 cycles.
3. The typical chip programming time is cCoCnsiderably less than the maximum chip programming time listed, since most bytes program faster
than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set I/O5 = 1. See
the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1 for further
information on command definitions.
6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaranteed.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F128K32
Rev. 2.0 5/03
17
AUSTIN [ AUSTIN SEMICONDUCTOR ]
