FLASH
AS8F128K32
Austin Semiconductor, Inc.
FIGURE 12: Toggle Bit Timings (During Embedded Algorithms)
NOTES: VA = Valid address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
*applies to every 8th byte.
AC CHARACTERISTICS: Erase and Program Operations, Alternate CEx\
Controlled Writes
SYMBOL
PARAMETER
JEDEC Standard DESCRIPTION -60 -70 -90 -120 -150 UNIT
1
t
t
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
TYP
TYP
60 70 90 120 150 ns
Write Cycle Time
AVAV
WC
0
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
AVEL
ELAX
AS
AH
DS
DH
t
45 45 45 50 50
t
t
t
30 30 45 50 50
DVEH
EHDX
0
t
1
0
t
Output Enable Setup Time
OES
0
Read Recover Time Before Write
WEx\ Setup Time
t
t
GHEL
GHEL
0
t
t
t
t
EHWH
EHWH
WS
WH
0
WEx\ Hold Time
CEx\ Pulse Width
t
t
30 35 45 50 50
ELEH
CP
20
14
CEx\ Pulse Width High
t
t
CPH
EHEL
2
t
t
t
t
Byte Programming Operation
WHWH1
WHWH2
WHWH1
WHWH2
2
1.0
Chip/Sector Erase Operation
NOTES:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F128K32
Rev. 2.0 5/03
16
AUSTIN [ AUSTIN SEMICONDUCTOR ]
