EEPROM
AS58LC1001
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
I/O0
I/O7
Ready/Busy
High Voltage Generator
I/O Buffer
and
OE\
Input Latch
Control Logic and Timing
CE\
WE\
RES\
A0
A6
Y Gating
Y Decoder
Address
Buffer and
Latch
X Decoder
Memory Array
A7
A16
Data Latch
MODE SELECTION
CE\
OE\
WE\
RES\
RDY/BUSY\
I/O
MODE
READ
VIL
VIL
VIH
VH
DOUT
High-Z
High-Z
High-Z
High-Z
STANDBY
WRITE
VIH
VIL
VIL
X
X
X
High-Z
DIN
VIH
VIH
VIL
VIH
VIH
X
VH
VH
DESELECT
High-Z
WRITE
X
X
X
X
X
---
---
---
---
INHIBIT
VIL
DATA
Data Out
(I/O7)
VIL
X
VIL
X
VIH
X
VH
VIL
VOL
POLLING
PROGRAM
High-Z
High-Z
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS58LC1001
Rev. 1.0 12/08
2
AUSTIN [ AUSTIN SEMICONDUCTOR ]
