SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
This is shown in Figure 7 for CAS latencies of two and three;
data element n + 3 is either the last of a burst of four or the last
desired of a longer burst. The 64Mb SDRAM uses a pipelined
architecture and therefore does not require the 2n rule
associated with a prefetch architecture. A READ command can
be initiated on any clock cycle following a previous READ
command. Full-speed random read accesses can be performed
to the same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
T6
T0
T1
T2
T3
T4
T5
CLK
NOP
NOP
NOP
NOP
NOP
READ
READ
COMMAND
X=1 cycle
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT
n+2
DOUT
n+1
DOUT
n
DOUT
n+3
DOUT
b
CAS Latency = 2
T7
T6
T0
T1
T2
T3
T4
T5
CLK
NOP
NOP
READ
NOP
NOP
READ
NOP
NOP
COMMAND
X=2 cycle
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT
n+2
DOUT
n+1
DOUT
n
DOUT
n+3
DOUT
b
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DON’T CARE
Figure 7
CONSECUTIVE READ BURSTS
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 2.1 6/05
14
AUSTIN [ AUSTIN SEMICONDUCTOR ]
