SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
READ --WITHOUT AUTO PRECHARGE1
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CL
CLK
CKE
t
t
CK
CH
t
t
t
CKS
CKH
t
CMS
CMH
PRECHARGE
ACTIVE
NOP
READ
NOP
NOP
NOP
ACTIVE
NOP
COMMAND
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AS
AH
A0-A9,
A11
COLUMN m2
ROW
ROW
t
t
AH
AS
ALL BANKS
SINGLE BANK
BANK
A10
BA0, BA1
DQ
ROW
ROW
t
t
DISABLE AUTO PRECHARGE
AS
AH
BANK
BANK
BANK
t
t
t
t
t
t
AC
AC
AC
t
t
AC
OH
OH
OH
OH
DOUT
m
DOUT m+2
DOUT m+1
DOUT m+3
t
t
LZ
HZ
t
t
CAS Latency
RCD
RP
t
RAS
t
RC
Don’t Care
Undefined
TIMING PARAMETERS
-8
-10
-8
-10
MIN
MAX
6.5
MIN
MAX
MIN
1
MAX
MIN
1
MAX
SYMBOL*
tAC(3)
UNITS
ns
SYMBOL*
UNITS
tCMH
tCMS
tHZ(3)
tHZ(2)
tLZ
7
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAC(2)
tAH
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
3
1
2
1
3
6
7
8
tAS
10
tCH
3
3.5
3.5
10
15
1
1
1
tCL
tOH
3
2.5
50
80
20
24
2.5
60
90
30
30
tCK(3)
tCK(2)
tCKH
tCKS
tRAS
tRC
tRCD
tRP
8
80,000
80,000
12
1
2
3
* CAS latency indicated in parentheseses.
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A8, A9 and A11 = “Don’t Care.”
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 1.5 10/01
39
AUSTIN [ AUSTIN SEMICONDUCTOR ]
