SDRAM
Austin Semiconductor, Inc.
GENERAL DESCRIPTION
The 512Mb SDRAM is a high-speed CMOS, dynamic ran-
dom-access memory containing 536, 870, 912 bits. It is inter-
nally configured as a quad-bank DRAM with a synchronous
interface (all signals are registered on the positive edge of the
clock signal, CLK). Each of the 67,108,864-bit banks is orga-
nized as 8,192 rows by 1024 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence. Ac-
cesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A12 select the row). The address bits
registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4, or 8 locations, or the full page, with a
burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence.
The 512Mb SDRAM uses an internal pipelined architec-
ture to achieve high-speed operation. This architecture is com-
patible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle
to achieve a high-speed, fully random operation. Precharging
one bank while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-speed, ran-
dom-access operation.
The 512Mb SDRAM is designed to operate in 3.3V memory
systems. An auto refresh mode is provided, along with a power-
saving, power-down mode. All inputs and outputs are LVTTL-
compatible.
SDRAMs offer substantial advances in DRAM operating
performance, including the ability to synchronously burst data
at a high data rate with automatic column-address generation,
the ability to interleave between internal banks to hide precharge
time and the capability to randomly change column addresses
on each clock cycle during a burst access.
AS4SD32M16
FUNCTIONAL BLOCK DIAGRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
COMMAND
DECODE
MODE REGISTER
REFRESH 13
COUNTER
12
13
ROW-
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
8192
LATCH
&
DECODER
BANK0
MEMORY
ARRAY
(8,192 x 1,024 x 16)
2
2
DQML,
DQMH
SENSE AMPLIFIERS
16
16384
DATA
OUTPUT
REGISTER
2
A0–A12,
BA0, BA1
ADDRESS
REGISTER
BANK
CONTROL
LOGIC
15
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
16
1024
(x16)
DATA
INPUT
REGISTER
16
DQ0–
DQ15
2
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
10
10
AS4SD32M16
Rev. 1.1 3/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
AUSTIN [ AUSTIN SEMICONDUCTOR ]
