SDRAM
AS4SD2M32
Austin Semiconductor, Inc.
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-length READ
burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be
maintained. The first data element from the new burst follows
either the last element of a complete burst or the last desired
data element of a longer burst that is being truncated. The new
READ command should be issued x cycles before the clock
edge at which the last desired data element is valid, where x
equals the CAS latency minus one. This is shown in Figure 7
for CAS latencies of two and three; data element n+3 is either
the last of a burst of four or the last desired of a longer burst.
The 64Mb SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch architec-
ture. A READ command can be initiated on any clock cycle
following a previous READ command. Full-speed random read
accesses can be performed to the same bank, as shown in Fig-
ure 8, or each subsequent READ may be performed to different
bank.
READs
READ bursts are initiated with a READ command, as shown
in Figure 5.
The starting column and bank addresses are provided with
the READ command, and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled, the
row being accessed is precharged at the completion of the burst.
For the generic READ commands used in the following
illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the
starting column address will be available following the CAS
latency after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 6
shows general timing for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands
have been initiated, the DQs will go High-Z. A full-page burst
will continue until terminated. (At the end of the page, it will
wrap to the start address and continue.)
FIGURE 6: CAS Latency
FIGURE 5: READ Command
CLK
CKE
CS\
RAS\
CAS\
WE\
A0-A7
A8, A9
A10
BA0, 1
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD2M32
Rev. 1.0 1/08
10
AUSTIN [ AUSTIN SEMICONDUCTOR ]
