iPEM
2.4Gb SDRAM-DDR
AS4DDR32M72PBG1
Austin Semiconductor, Inc.
Althꢀꢁgh nꢀt a JEDEC reqꢁirement, tꢀ prꢀvide fꢀr fꢁtꢁre
fꢁnctiꢀnality featꢁres, CKE mꢁst be active (High) dꢁring the
AUTO REFRESH periꢀd. TheAUTO REFRESH periꢀd begins
ohen the AUTO REFRESH cꢀmmand is registered and ends
tRFC later.
AUTO PRECHARGE
AUTO PRECHARGE is a featꢁre ohich perfꢀrms the same
individꢁal-bank PRECHARGE fꢁnctiꢀn described abꢀve, bꢁt
oithꢀꢁt reqꢁiring an explicit cꢀmmand. This is accꢀmplished
by ꢁsing A10 tꢀ enable AUTO PRECHARGE in cꢀnjꢁnctiꢀn
oith a specific READ ꢀr WRITE cꢀmmand. A precharge ꢀf
the bank/rꢀo that is addressed oith the READ ꢀr WRITE
cꢀmmand is aꢁtꢀmatically perfꢀrmed ꢁpꢀn cꢀmpletiꢀn ꢀf
the READ ꢀr WRITE bꢁrst. AUTO PRECHARGE is
nꢀnpersistent in that it is either enabled ꢀr disabled fꢀr each
individꢁal READ ꢀr WRITE cꢀmmand. The device sꢁppꢀrts
cꢀncꢁrrent aꢁtꢀ precharge if the cꢀmmand tꢀ the ꢀther bank
dꢀes nꢀt interrꢁpt the data transfer tꢀ the cꢁrrent bank.
SELF REFRESH*
The SELF REFRESH cꢀmmand can be ꢁsed tꢀ retain data
in the DDR SDRAM, even if the rest ꢀf the system is pꢀoered
dꢀon. When in the self refresh mꢀde, the DDR SDRAM retains
data oithꢀꢁt external clꢀcking. The SELF REFRESH
cꢀmmand is initiated like an AUTO REFRESH cꢀmmand
except CKE is disabled (LOW). The DLL is aꢁtꢀmatically
disabled ꢁpꢀn entering SELF REFRESH and is aꢁtꢀmatically
enabled ꢁpꢀn exiting SELF REFRESH (200 clꢀck cycles mꢁst
then ꢀccꢁr befꢀre a READ cꢀmmand can be issꢁed). Inpꢁt
signals except CKE are “Dꢀn’t Care” dꢁring SELF REFRESH.
The prꢀcedꢁre fꢀr exiting self refresh reqꢁires a seqꢁence
ꢀf cꢀmmands. First, CLK mꢁst be stable priꢀr tꢀ CKE gꢀing
back HIGH. Once CKE is HIGH, the DDR SDRAM mꢁst have
NOP cꢀmmands issꢁed fꢀr tXSNR, becaꢁse time is reqꢁired
AUTO PRECHARGE ensꢁres that the precharge is initiated
at the earliest valid stage oithin a bꢁrst. This “earliest valid
stage” is determined as if an explicit precharge cꢀmmand
oas issꢁed at the earliest pꢀssible time, oithꢀꢁt viꢀlating
tRAS (MIN).The ꢁser mꢁst nꢀt issꢁe anꢀther cꢀmmand tꢀ the
same bank ꢁntil the precharge time (tRP) is cꢀmpleted. This
is determined as if an explicit PRECHARGE cꢀmmand oas
issꢁed at the earliest pꢀssible time, oithꢀꢁt viꢀlating tRAS
(MIN).
fꢀr the cꢀmpletiꢀn ꢀf any internal refresh in prꢀgress.
A
simple algꢀrithm fꢀr meeting bꢀth refresh and DLL
reqꢁirements is tꢀ apply NOPs fꢀr 200 clꢀck cycles befꢀre
applying any ꢀther cꢀmmand.
* Self refresh available in cꢀmmercial and indꢁstrial temperatꢁres ꢀnly.
BURST TERMINATE
The BURST TERMINATE cꢀmmand is ꢁsed tꢀ trꢁncate READ
bꢁrsts (oith aꢁtꢀ precharge disabled). The mꢀst recently
registered READ cꢀmmand priꢀr tꢀ the BURST TERMINATE
cꢀmmand oill be trꢁncated. The ꢀpen page ohich the READ
bꢁrst oas terminated frꢀm remains ꢀpen.
AUTO REFRESH
AUTO REFRESH is ꢁsed dꢁring nꢀrmal ꢀperatiꢀn ꢀf the
DDR SDRAM and is analꢀgꢀꢁs tꢀ CAS#-BEFORE-RAS#
(CBR) REFRESH in cꢀnventiꢀnal DRAMs. This cꢀmmand is
nꢀnpersistent, sꢀ it mꢁst be issꢁed each time a refresh is
reqꢁired.
The addressing is generated by the internal refresh
cꢀntrꢀller. This makes the address bits “Dꢀn’t Care” dꢁring
an AUTO REFRESH cꢀmmand. Each DDR SDRAM reqꢁires
AUTO REFRESH cycles at an average interval ꢀf 7.8125µs
(maximꢁm).
Tꢀ allꢀo fꢀr imprꢀved efficiency in schedꢁling and soitching
betoeen tasks, sꢀme flexibility in the absꢀlꢁte refresh interval
is prꢀvided. Amaximꢁm ꢀf eightAUTO REFRESH cꢀmmands
can be pꢀsted tꢀ any given DDR SDRAM, meaning that the
maximꢁm absꢀlꢁte interval betoeen any AUTO REFRESH
cꢀmmand and the next AUTO REFRESH cꢀmmand is 9 x
7.8125µs (70.3µs). This maximꢁm absꢀlꢁte interval is tꢀ
allꢀo fꢁtꢁre sꢁppꢀrt fꢀr DLL ꢁpdates internal tꢀ the DDR
SDRAM tꢀ be restricted tꢀ AUTO REFRESH cycles, oithꢀꢁt
allꢀoing excessive drift in tAC betoeen ꢁpdates.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4DDR32M72PBG1
Rev. 0.1 06/09
9
AUSTIN [ AUSTIN SEMICONDUCTOR ]
