iPEM
2.4Gb SDRAM-DDR
AS4DDR32M72PBG1
Austin Semiconductor, Inc.
TABLE 1 - BURST DEFINITION
REGISTER DEFINITION
Burst
Starting Column
Order of Accesses Within a Burst
MODE REGISTER
Length
Address
Type = Sequential
Type = Interleaved
The Mꢀde Register is ꢁsed tꢀ define the specific mꢀde ꢀf
ꢀperatiꢀn ꢀf the DDR SDRAM. This definitiꢀn inclꢁdes the
selectiꢀn ꢀf a bꢁrst length, a bꢁrst type, a CAS latency, and
an ꢀperating mꢀde, as shꢀon in Figꢁre 3. The Mꢀde Register
is prꢀgrammed via the MODE REGISTER SET cꢀmmand
(oith BA0 = 0 and BA1 = 0) and oill retain the stꢀred
infꢀrmatiꢀn ꢁntil it is prꢀgrammed again ꢀr the device lꢀses
pꢀoer. (Except fꢀr bit A8 ohich is self clearing).
A0
2
4
0
1
0-1
1-0
0-1
1-0
A1 A0
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
A2 A1 A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Reprꢀgramming the mꢀde register oill nꢀt alter the cꢀntents
ꢀf the memꢀry, prꢀvided it is perfꢀrmed cꢀrrectly. The Mꢀde
Register mꢁst be lꢀaded (relꢀaded) ohen all banks are idle
and nꢀ bꢁrsts are in prꢀgress, and the cꢀntrꢀller mꢁst oait
the specified time befꢀre initiating the sꢁbseqꢁent ꢀperatiꢀn.
Viꢀlating either ꢀf these reqꢁirements oill resꢁlt in
ꢁnspecified ꢀperatiꢀn. Mꢀde register bits A0-A2 specify the
bꢁrst length, A3 specifies the type ꢀf bꢁrst (seqꢁential ꢀr
interleaved), A4-A6 specify the CAS latency, and A7-A12
specify the ꢀperating mꢀde.
8
NOTES:
1. Fꢀr a bꢁrst length ꢀf toꢀ, A1-Ai select toꢀ-data-element blꢀck;
A0 selects the starting cꢀlꢁmn oithin the blꢀck.
2. Fꢀr a bꢁrst length ꢀf fꢀꢁr, A2-Ai select fꢀꢁr-data-element blꢀck;
A0-1 select the starting cꢀlꢁmn oithin the blꢀck.
3. Fꢀr a bꢁrst length ꢀf eight, A3-Ai select eight-data-element blꢀck;
A0-2 select the starting cꢀlꢁmn oithin the blꢀck.
4. Whenever a bꢀꢁndary ꢀf the blꢀck is reached oithin a given
seqꢁence abꢀve, the fꢀllꢀoing access oraps oithin the blꢀck.
BURST LENGTH
Read and orite accesses tꢀ the DDR SDRAM are bꢁrst
ꢀriented, oith the bꢁrst length being prꢀgrammable, as
shꢀon in Figꢁre 3. The bꢁrst length determines the maximꢁm
nꢁmber ꢀf cꢀlꢁmn lꢀcatiꢀns that can be accessed fꢀr a given
READ ꢀr WRITE cꢀmmand. Bꢁrst lengths ꢀf 2, 4 ꢀr 8
lꢀcatiꢀns are available fꢀr bꢀth the seqꢁential and the
interleaved bꢁrst types.
READ LATENCY
The READ latency is the delay, in clꢀck cycles, betoeen the
registratiꢀn ꢀf a READ cꢀmmand and the availability ꢀf the
first bit ꢀf ꢀꢁtpꢁt data. The latency can be set tꢀ 2 ꢀr 2.5
clꢀcks.
Reserved states shꢀꢁld nꢀt be ꢁsed, as ꢁnknꢀon ꢀperatiꢀn
ꢀr incꢀmpatibility oith fꢁtꢁre versiꢀns may resꢁlt.
If a READ cꢀmmand is registered at clꢀck edge n, and the
latency is m clꢀcks, the data oill be available by clꢀck edge
n+m. Table 2 belꢀo indicates the ꢀperating freqꢁencies at
ohich each CAS latency setting can be ꢁsed.
When a READ ꢀr WRITE cꢀmmand is issꢁed, a blꢀck ꢀf
cꢀlꢁmns eqꢁal tꢀ the bꢁrst length is effectively selected. All
accesses fꢀr that bꢁrst take place oithin this blꢀck, meaning
that the bꢁrst oill orap oithin the blꢀck if a bꢀꢁndary is
reached. The blꢀck is ꢁniqꢁely selected by A1-Ai ohen the
bꢁrst length is set tꢀ toꢀ; by A2-Ai ohen the bꢁrst length is
set tꢀ fꢀꢁr (ohere Ai is the mꢀst significant cꢀlꢁmn address
fꢀr a given cꢀnfigꢁratiꢀn); and by A3-Ai ohen the bꢁrst length
is set tꢀ eight. The remaining (least significant) address
bit(s) is (are) ꢁsed tꢀ select the starting lꢀcatiꢀn oithin the
blꢀck. The prꢀgrammed bꢁrst length applies tꢀ bꢀth READ
and WRITE bꢁrsts.
Reserved states shꢀꢁld nꢀt be ꢁsed as ꢁnknꢀon ꢀperatiꢀn
ꢀr incꢀmpatibility oith fꢁtꢁre versiꢀns may resꢁlt.
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
CAS
SPEED
-10
LATENCY=2 LATENCY=2.5
75
100
100
100
100
125
133
166
-8
BURST TYPE
-75
Accesses oithin a given bꢁrst may be prꢀgrammed tꢀ be
either seqꢁential ꢀr interleaved; this is referred tꢀ as the
bꢁrst type and is selected via bit M3. The ꢀrdering ꢀf accesses
oithin a bꢁrst is determined by the bꢁrst length, the bꢁrst
type and the starting cꢀlꢁmn address, as shꢀon in Table 1.
-6
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4DDR32M72PBG1
Rev. 0.1 06/09
5
AUSTIN [ AUSTIN SEMICONDUCTOR ]
