iPEM
4.8 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR264M72PBG
DDRII ICC SPECIFICATIONS AND CONDITIONS
667 MHZ
-3
533 MHZ
400 MHZ
-5
Parameter
Symbol
-38
Units
Operating Current: One bank active-precharge
tCL=tCK(ICC), tRC=tRC(ICC), tRAS=tRAS MIN(ICC); CKE is
HIGH, CS\ is HIGH between valid commands; Address bus
switching, Data bus switching
ICC0
600
750
35
550
500
600
35
mA
Operating Current: One bank active-READ-precharge
current
IOUT=0ma; BL=4, CL=CL(ICC), AL=0; tCK = tCK(ICC), tRC-
tRC(ICC), tRAS=tRAS MIN(ICC), tRCD=tRCD(ICC); CKE is
HIGH, CS\ is HIGH between valid commands; Address bus is
switching; Data bus is switching
ICC1
ICC2P
ICC2Q
ICC2N
ICC3P
650
mA
mA
mA
mA
mA
Precharge POWER-DOWN current
All banks idle; tCK-tCK(ICC); CKE is LOW; Other control and
address bus inputs are stable; Data bus inputs are floating
35
Precharge quiet STANDBY current
All banks idle; tCK=tCK(ICC); CKE is HIGH, CS\ is HIGH;
Other control and address bus inputs are stable; Data bus
inputs are floating
275
300
225
250
175
200
Precharge STANDBY current
All banks idle; tCK-=tCK(ICC); CKE is HIGH, CS\ is HIGH;
Other control and address bus inputs are switching; Data bus
inputs are switching
Active POWER-DOWN current
MRS[12]=0
150
50
125
50
115
50
All banks open; tCK=tCK(ICC); CKE is LOW;
Other control and address inputs are stable; Data
MRS[12]=1
bus inputs are floating
Active STANDBY current
All banks open; tCK=tCK(ICC), tRAS MAX(ICC),
tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are
switching; Data bus inputs are switching
ICC3N
ICC4W
300
850
250
700
200
600
mA
mA
Operating Burst WRITE current
All banks open, continuous burst writes; BL=4, CL=CL(ICC),
tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid
commands; Address bus inputs are switching; Data bus
Operating Burst READ current
All banks open, continuous burst READS, Iout=0mA; BL=4,
CL=CL(ICC), AL=0; tCL=tCK(ICC), tRAS=tRAS MAX(ICC),
tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid
commands; Address and Data bus inputs switching
ICC4R
850
700
600
mA
Burst REFRESH current
tCK=tCK(ICC); refresh command at every iRFC(ICC) interval;
CKE is HIGH, CS\ is HIGH Between valid commands;
Address bus inputs are switching; Data bus inputs are
switching
ICC5
ICC6
1100
1000
900
mA
mA
Self REFRESH current
CK and CK\ at 0V; CKE </=0.2V; Other contro, address and
data inputs are floating
35
35
35
Operating bank Interleave READ current:
All bank interleaving READS, IOUT = 0mA; BL=4,
CL=CL(ICC), AL=tRCD(ICC)-1xtCK(ICC); tCK=tCK(ICC),
tRC=tRC(ICC), tRRD=tRRD(ICC); CKE is HIGH, CS\ is HIGH
between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
ICC7
1500
1400
1300
mA
Austin Semiconductor, Inc.
●
Austin, Texas
●
512.339.1188
●
www.austinsemiconductor.com
AS4DDR264M72PBG
Rev. 1.5 11/07
23
AUSTIN [ AUSTIN SEMICONDUCTOR ]
