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AS4DDR264M72PBG-5/ET 参数 Datasheet PDF下载

AS4DDR264M72PBG-5/ET图片预览
型号: AS4DDR264M72PBG-5/ET
PDF下载: 下载PDF文件 查看货源
内容描述: 64Mx72 DDR2 SDRAM集成塑封微电路 [64Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 内存集成电路动态存储器双倍数据速率
文件页数/大小: 28 页 / 257 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
 浏览型号AS4DDR264M72PBG-5/ET的Datasheet PDF文件第17页浏览型号AS4DDR264M72PBG-5/ET的Datasheet PDF文件第18页浏览型号AS4DDR264M72PBG-5/ET的Datasheet PDF文件第19页浏览型号AS4DDR264M72PBG-5/ET的Datasheet PDF文件第20页浏览型号AS4DDR264M72PBG-5/ET的Datasheet PDF文件第22页浏览型号AS4DDR264M72PBG-5/ET的Datasheet PDF文件第23页浏览型号AS4DDR264M72PBG-5/ET的Datasheet PDF文件第24页浏览型号AS4DDR264M72PBG-5/ET的Datasheet PDF文件第25页  
iPEM  
4.8 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR264M72PBG  
DC OPERATING CONDITIONS  
All Voltages referenced to Vss  
Parameter  
Supply Voltage  
Symbol  
VCC  
MIN  
1.7  
TYP  
1.8  
MAX  
1.9  
Units  
Notes  
V
V
V
V
1
4
2
3
VCCQ  
VREF  
VTT  
I/O Supply Voltage  
1.7  
1.8  
1.9  
I/O Reference Voltage  
I/O Termination Voltage  
0.49 x VCCQ  
VREF - 0.04  
0.50 x VCCQ  
VREF  
0.51 x VCCQ  
VREF + 0.04  
Notes:  
1. VCC VCCQ must track each other. VCCQ must be less than or equal to VCC.  
2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not  
exceed ± 1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of VREF. This measurement is to be taken at the  
nearest VREF bypass capacitor.  
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track  
variations in the DC level of VREF.  
4. VCCQ tracks with VCC track with VCC.  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
VCC  
Parameter  
Voltage on VCC pin relative to VSS  
Voltage on VCCQ pin relative to V  
Min  
-1.0  
Max  
2.3  
Unit  
V
VCCQ  
-0.5  
2.3  
V
SS  
VIN, VOUT  
TSTG  
Voltage on any pin relative to V  
-0.5  
2.3  
V
oC  
oC  
SS  
Storage Temperature  
-55.0  
-55.0  
125.0  
125.0  
TCASE  
Device Operating Temperature  
ADDR, BAx  
-10.0  
10.0  
uA  
uA  
RAS\, CAS\, WE\, CS\,  
CKE, DM, DQS, DQS\,  
RDQS  
-5  
5
Input Leakage current; Any input 0V<V <VCC  
IN  
;
VREF =  
II  
.5XVCCQ; Other balls not under test = 0V  
CK, CK\  
DM  
-5  
-5  
5
5
uA  
uA  
OV ” VOUT ” VDDQ, DQ & ODT Disabled  
VREF Leakage Current  
IOZ  
-5  
5
uA  
uA  
IVREF  
-10  
10  
INPUT / OUTPUT CAPACITANCE  
TA = 25oC, f = 1 MHz, VCC = VCCQ = 1.8V  
Parameter  
Symbol  
Max  
Unit  
CADDR  
Input capacitance (A0-A12, BA2-BA0)  
Input capacitance (CS#, RAS#, CAS#, WE#, CKE, ODT)  
Input capacitance CK, CK#  
28  
10  
8
pF  
pF  
pF  
pF  
pF  
CIN1  
CIN2  
CIN3  
COUT  
Input capacitance DM, DQS, DQS#  
Input capacitance DQ0-71  
10  
12  
Austin Semiconductor, Inc.  
Austin, Texas  
512.339.1188 www.austinsemiconductor.com  
AS4DDR264M72PBG  
Rev. 1.5 11/07  
21  
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