iPEM
4.8 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR264M72PBG1
AC OPERATING SPECIFICATIONS (CONTINUED)
-3
667Mbps
-38
-5
533Mbps
400Mbps
Parameter
Symbol
tIPW
MIN
MAX
MIN
MAX
MIN
MAX
Units
tCK
ps
Address and Control input puslse width for each input
Address and Control input setup time
0.6
0.6
0.6
tISJEDEC
200
250
350
tIHJEDEC
Address and Control input hold time
CAS\ to CAS\ command delay
275
2
375
2
475
2
ps
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
tCCD
tRC
ACTIVE to ACTIVE command (same bank)
ACTIVE bank a to ACTIVE bank b Command
ACTIVE to READ or WRITE delay
4-Bank activate period
55
55
10
15
50
55
10
15
50
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
10
15
50
ACTIVE to PRECHARGE
40
700001
40
7.5
700001
40
7.5
700001
Internal READ to PRECHARGE command delay
WRITE recovery time
7.5
15
15
15
Auto PRECHARGE WRITE recovery+PRECHARGE time
Internal WRITE to READ command delay
PRECHARGE command period
tDAL
tWTR
tRP
tWR + tRP
7.5
15
tWR + tRP
7.5
tWR + tRP
10
15
15
PRECHARGE ALL command period
LOAD MODE, command Cycle time
CKE LOW to CK, CK\ uncertainty
tRPA
tMRD
tDELAY
tRP+tCL
2
tRP+tCL
2
tRP+tCL
2
tIS + tCL + tIH
tIS + tCL + tIH
tIS + tCL + tIH
REFRESH to ACTIVE or REFRESH to REFRESH
command Interval
70000 1
70000 1
70000 1
tRFC
127
127
127
ns
tREFIIT
tREFIET
tREFIXT
Average periodic REFRESH interval [Industrial temp]
7.8
5.9
3.9
7.8
5.9
3.9
7.8
5.9
3.9
us
us
us
Average periodic REFRESH interval [Enhanced temp]
Average periodic REFRESH interval [Military temp]
Exit SELF REFRESH to non READ command
tRFC(min)+1
0
tRFC(min)+1
0
tRFC(min)+1
0
tXSNR
tXSRD
tISXR
ns
tCK
ps
Exit SELF REFRESH to READ command
Exit SELF REFRESH timing reference
200
tIS
200
tIS
200
tIS
ODT turn-on delay
ODT turn-on delay
ODT turn-off delay
ODT turn-off delay
tAOND
tAOND
tAOPD
tAOF
2
2
2
2
2
2
tCK
ps
tAC(max)+
700
tAC(max)+
1000
tAC(max)+
1000
tAC(min)
2.5
tAC(min)
2.5
tAC(min)
2.5
2.5
tAC(max)+
600
2.5
tAC(max)+
600
2.5
tAC(max)+
600
tCK
ps
tAC(min)
tAC(min)
tAC(min)
2 x tCK +
tAC(max)+
1000
2 x tCK +
tAC(max)+
1000
2 x tCK +
tAC(max)+
1000
tAC(min) +
2000
tAC(min) +
2000
tAC(min) +
2000
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
tAOFPD
ps
ps
2.5 x tCK +
tAC(max)+
1000
2.5 x tCK +
tAC(max)+
1000
2.5 x tCK +
tAC(max)+
1000
tAC(min) +
2000
tAC(min) +
2000
tAC(min) +
2000
ODT to power-down entry latency
tANPD
tAXPD
tMOD
tXARD
tSARDS
tXP
3
8
3
8
3
8
tCK
tCK
ns
ODT power-down exit latency
ODT enable from MRS command
12
2
12
2
12
2
Exit active POWER-DOWN to READ command, MR[12]=0
Exit active POWER-DOWN to READ command, MR[12]=1
Exit PRECHARGE POWER-DOWN to any non READ
CKE Min. HIGH/LOW time
tCK
tCK
tCK
tCK
7 - AL
2
6 - AL
2
6 - AL
2
tCLE
3
3
3
Note 1: Max value reduced to 10,000ns at 125oC
Austin Semiconductor, Inc.
● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com
AS4DDR264M72PBG1
Rev. 3.0 6/09
25