iPEM
4.2 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR264M64PBG1
MODE REGISTER (MR)
FIGURE 5 – MODE REGISTER (MR) DEFINITION
The mode register is used to define the specific mode of
operation of the DDR2 SDRAM. This definition includes the
selection of a burst length, burst type, CL, operating mode,
DLL RESET, write recovery, and power-down mode, as
shown in Figure 5. Contents of the mode register can be
altered by re-executing the LOAD MODE (LM) command. If
the user chooses to modify only a subset of the MR variables,
all variables (M0–M14) must be programmed when the
command is issued.
2
1
2
1
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
16 15 14
n
12 11 10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
1
0
MR
0
PD
WR
DLL TM CAS# Latency BT Burst Length
M2 M1 M0
Burst Length
Reserved
Reserved
4
M12 PD Mode
Mode
Normal
Test
M7
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Fast exit
(normal)
1
1
Slow exit
The mode register is programmed via the LM command
(bits BA2–BA0 = 0, 0,0) and other bits (M13–M0) will retain
the stored information until it is programmed again or the
device loses power (except for bit M8, which is selfclearing).
Reprogramming the mode register will not alter the contents
of the memory array, provided it is performed correctly.
(low power)
8
DLL Reset
No
M8
0
Reserved
Reserved
Reserved
Reserved
1
Yes
Write Recovery
M11 M10 M9
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
Burst Type
Sequential
Interleaved
M3
0
The LM command can only be issued (or reissued) when all
banks are in the precharged state (idle state) and no bursts
are in progress. The controller must wait the specified time
tMRD before initiating any subsequent operations such as
an ACTIVE command. Violating either of these requirements
will result in unspecified operation.
1
CAS Latency (CL)
M6 M5 M4
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
M15 M16
Mode Register Definition
Mode register (MR)
3
4
5
6
7
BURST LENGTH
0
0
1
1
0
1
0
1
Burst length is defined by bits M0–M3, as shown in Figure
5. Read and write accesses to the DDR2 SDRAM are burst-
oriented, with the burst length being programmable to either
four or eight. The burst length determines the maximum
number of column locations that can be accessed for a given
READ or WRITE command.
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
Notes:
1.A13 Not used on this part, and must be programmed to ‘0’ on
this part.
2.BA2 must be programmed to “0” and is reserved for future use.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A2–Ai when BL =
4 and by A3–Ai when BL = 8 (where Ai is the most significant
column address bit for a given configuration). The remaining
(least significant) address bit(s) is (are) used to select the
starting location within the block. The programmed burst
length applies to both READ and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved. The burst type is selected
via bit M3, as shown in Figure 5. The ordering of accesses
within a burst is determined by the burst length, the burst
type, and the starting column address, as shown in Table
2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst
mode only. For 8-bit burst mode, full interleave address
ordering is supported; however, sequential address ordering
is nibble-based.
Austin Semiconductor, Inc.
● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com
AS4DDR264M64PBG1
Rev. 0.5 06/08
7
AUSTIN [ AUSTIN SEMICONDUCTOR ]
