iPEM
4.2 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR264M64PBG1
Description
BGA Locations
Symbol
Type
P6
ODT
CNTL Input On-Die-Termination: Registered High enables on data bus termination
CNTL Input Differential input clocks, one set for each x16bits
C9,C10,D10,D11,T1,T2,
U2,U3
CKx, CKx\
T8
CKE
CS\
CNTL Input Clock enable which activates all on silicon clocking circuitry
CNTL Input Chip Selects, one for each 16 bits of the data bus width
V5
U5
RAS\
CNTL Input Command input which along with CAS\, WE\ and CS\ define operations
CNTL Input Command input which along with RAS\, WE\ and CS\ define operations
CNTL Input Command input which along with RAS\, CAS\ and CS\ define operations
CNTL Input One Data Mask cntl. for each upper 8 bits of a x16 word
U6
CAS\
T9
WE\
G5,H1,M11,N7
UDMx
LDMx
UDQSx
UDQSx\
LDQSx
LDQSx\
Ax
F1,F2,P10,P11
CNTL Input One Data Mask cntl. For each lower 8 bits of a x16 word
H9,H10,M2,M3
CNTL Input Data Strobe input for upper byte of each x16 word
H7,H11,M1,M5
CNTL Input Differential input of UDQSx, only used when Differential DQS mode is enabled
CNTL Input Data Strobe input for lower byte of each x16 word
E8,E9,R3,R4,T6
F10,F11,P1,P2
CNTL Input Differential input of LDQSx, only used when Differential DQS mode is enabled
J2,J3,J4,J8,J9,J10,K2,
K3,K9,L2,L3,L4,L9,L10
J10
Input
Array Address inputs providing ROW addresses for Active commands, and
the column address and auto precharge bit (A10) for READ/WRITE commands
RFU
BA0,BA1,BA2
DQx
Future Input
Input
L8,K10,E5
Bank Address inputs
C8,D1,D2,D7,D8,D9,E1,
E2,E3,E7,E10,E11,F3,
F4,F5,F7,F8,F9,G1,G2,
G3,G4,G7,G8,G9,G10,
G11,H2,H3,H4,H5,H8,
M4,M7,M8,M9,M10,N1,
N2,N3,N4,N5,N8,N9,
N10,N11,P3,P4,P5,P7,
P8,P9,R1,R2,R5,R9,
R10,R11,T3,T4,T5,
T10,T11,U4
Input/Output Data bidirectional input/Output pins
K6
Vref
VCC
Supply
Supply
SSTL_18 Voltage Reference
Core Power Supply
A2,A4,A5,A7,A8,A10,
B1,B11,H6,J1,J5,J7,J11,
K4,K8,L1,L5,L7,L11,M6,
V1,V11,W2,W4,W5,
W7,W8,W10
A3,A6,A9,A11,B2,B10,
C1,C11,G6,J6,K1,K5,
K7,K11,L6,N6,U1,U11,
V2,V10,W1,W3,W6,
W9,W11
VSS
NC
Supply
Core Ground return
B3,B4,B5,B6,B7,B8,B9,
C2,C3,C4,C5,C6,C7,D3,
D4,D5,D6,E4,E5,F6,R6,
R7,R8.T6,T7,U7,U8,U9,
U10,V3,V4,V6,V7,V8,V9
A1
No connection
UNPOPULATED
Unpopulated ball matrix location (location registration aid)
Austin Semiconductor, Inc.
● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com
AS4DDR264M64PBG1
Rev. 0.5 06/08
3
AUSTIN [ AUSTIN SEMICONDUCTOR ]
