iPEM
4.2 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR264M64PBG1
TABLE 3 - TRUTH TABLE - DDR2 COMMANDS
CKE
BA2 thru
Function
CS#
RAS#
CAS#
WE#
A10
A9-A0
Notes
Previous Current
A12
A11
Cycle
Cycle
BA0
OP CODE
LOAD MODE
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
H
H
X
H
L
BA
2
REFRESH
X
X
X
X
X
X
X
X
SELF-REFRESH Entry
L
X
H
H
H
H
SELF-REFRESH exit
L
H
X
X
X
X
7
2
Single Bank Precharge
All banks PRECHARGE
Bank Activate
H
H
H
H
H
H
X
X
X
X
L
X
X
L
H
ROW ADDRESS
L
BA
Column
Address
Column
Address
Column
Address
Column
Address
Column
Address
Column
Address
Column
Address
Column
Address
WRITE
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
L
L
BA
BA
BA
BA
L
H
L
2,3
2,3
2,3
2,3
WRITE with auto precharge
READ
H
H
READ with auto precharge
L
NO OPERATION
H
H
X
X
L
H
H
L
H
X
X
H
X
H
H
X
X
H
X
H
H
X
X
H
X
H
X
X
X
X
X
X
X
X
Device DESELECT
POWER-DOWN entry
POWER-DOWN exit
H
L
L
X
X
X
X
X
X
X
X
4
4
H
L
H
Note: 1. All DDR2-SDRAM commands are defined by staes of CS#, RAS#, CAS#, WE#, and CKE a the
rising edge of the clock.
2. Bank addresses (BA) BA2-BA0 determine which bank is to be operated upon. BA during a LM
command selects which mode register is programmed.
3. Burst reads or writes at BL=4 cannot be terminated or interrupted.
4. The power down mode does not perform any REFRESH operations. The duration of power down
is therefore limited by the refresh requirements outlined in theAC parametric section.
5. The state of ODT does not effect the states described in this table. The ODT function is not available
during self refresh. See “On Die Termination (ODT)” for details.
6. “X” means “H or L” (but a defined logic level)
7. Self refresh exit is asynchronous.
Austin Semiconductor, Inc.
● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com
AS4DDR264M64PBG1
Rev. 0.5 06/08
14
AUSTIN [ AUSTIN SEMICONDUCTOR ]
