iPEM
4.2 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR264M64PBG1
POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AL) is supported to make the
command and data bus efficient for sustainable bandwidths
in DDR2 SDRAM. Bits E3–E5 define the value of AL, as
shown in Figure 7. Bits E3–E5 allow the user to program
the DDR2 SDRAM with an inverse AL of 0, 1, 2, 3, 4, 5 or 6
clocks. Reserved states should not be used as unknown
operation or incompatibility with future versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE
command to be issued prior to tRCD (MIN) with the
requirement that AL = tRCD (MIN). A typical application using
this feature would set AL = tRCD (MIN) - 1x tCK. The READ or
WRITE command is held for the time of the AL before it is
issued internally to the DDR2 SDRAM device. RL is controlled
by the sum of AL and CL; RL = AL+CL. Write latency (WL) is
equal to RL minus one clock; WL = AL + CL - 1 x t
.
CK
FIGURE 8 - EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
1
2
BA1 BA0 An1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
BA2
Extended mode
register (Ex)
16 15 14
n
12 11 10
9
8
7
6
0
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
SRT
MRS
0
0
E7
0
SRT Enable
E15 E14
Mode Register Set
Mode register (MR)
1X refresh rate (0°C to 85°C)
2X refresh rate (>85°C)
0
0
1
1
0
1
0
1
1
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
Notes:
1.E16 bit (BA2) must be programmed to “0” and is reserved for future use.
2.Mode bits (En) with corresponding address balls (An) greater than A12 are reserved for future use and must be programmed to “0.”
Austin Semiconductor, Inc.
● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com
AS4DDR264M64PBG1
Rev. 0.5 06/08
12
AUSTIN [ AUSTIN SEMICONDUCTOR ]
