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AS4DDR232M64PBGR-5/IT 参数 Datasheet PDF下载

AS4DDR232M64PBGR-5/IT图片预览
型号: AS4DDR232M64PBGR-5/IT
PDF下载: 下载PDF文件 查看货源
内容描述: 32Mx64 DDR2 SDRAM集成塑封微电路 [32Mx64 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 内存集成电路动态存储器双倍数据速率
文件页数/大小: 28 页 / 363 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
2.1 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR232M64PBG  
AC OPERATING SPECIFICATIONS (CONTINUED)  
-3  
-38  
-5  
333MHz/667Mbps 266MHz/567Mbps 200MHz/400Mbps  
Parameter  
Symbol  
tIPW  
MIN  
0.6  
MAX  
70000  
70000  
MIN  
0.6  
MAX  
70000  
70000  
MIN  
0.6  
MAX  
70000  
70000  
Units  
tCK  
ps  
Address and Control input puslse width for each input  
Address and Control input setup time  
tISJEDEC  
200  
250  
350  
tIHJEDEC  
Address and Control input hold time  
CAS\ to CAS\ command delay  
275  
2
375  
2
475  
2
ps  
ps  
ps  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
ns  
tCCD  
tRC  
ACTIVE to ACTIVE command (same bank)  
ACTIVE bank a to ACTIVE bank b Command  
ACTIVE to READ or WRITE delay  
4-Bank activate period  
55  
55  
55  
tRRD  
tRCD  
tFAW  
tRAS  
tRTP  
tWR  
10  
10  
10  
15  
15  
15  
50  
50  
50  
ACTIVE to PRECHARGE  
40  
10  
40  
Internal READ to PRECHARGE command delay  
WRITE recovery time  
7.5  
15  
7.5  
15  
7.5  
15  
Auto PRECHARGE WRITE recovery+PRECHARGE time  
Internal WRITE to READ command delay  
PRECHARGE command period  
tDAL  
tWTR  
tRP  
tWR + tRP  
7.5  
15  
tWR + tRP  
7.5  
15  
tWR + tRP  
10  
15  
PRECHARGE ALL command period  
LOAD MODE, command Cycle time  
CKE LOW to CK, CK\ uncertainty  
tRPA  
tMRD  
tDELAY  
tRP+tCL  
2
tRP+tCL  
2
tRP+tCL  
2
tIS + tCL + tIH  
tIS + tCL + tIH  
tIS + tCL + tIH  
REFRESH to ACTIVE or REFRESH to REFRESH  
command Interval  
tRFC  
105  
105  
105  
ns  
tREFIIT  
tREFIET  
tREFIXT  
Average periodic REFRESH interval [Industrial temp]  
7.8  
7.8  
3.9  
7.8  
3.9  
3.9  
us  
us  
us  
Average periodic REFRESH interval [Enhanced temp]  
Average periodic REFRESH interval [Military temp]  
Exit SELF REFRESH to non READ command  
TBD  
TBD  
TBD  
tRFC(min)+  
10  
tRFC(min)+  
10  
tRFC(min)+  
10  
tXSNR  
tXSRD  
tISXR  
ns  
tCK  
ps  
Exit SELF REFRESH to READ command  
Exit SELF REFRESH timing reference  
200  
tIS  
200  
tIS  
200  
tIS  
ODT turn-on delay  
ODT turn-on delay  
ODT turn-off delay  
ODT turn-off delay  
tAOND  
tAOND  
tAOPD  
tAOF  
2
2
tAC(max)+7  
00  
2
2
2
2
tCK  
ps  
tAC(max)+1  
000  
tAC(max)+1  
000  
tAC(min)  
tAC(min)  
tAC(min)  
2.5  
2.5  
tAC(max)+6  
00  
2.5  
2.5  
tAC(max)+6  
00  
2.5  
2.5  
tAC(max)+6  
00  
tCK  
ps  
tAC(min)  
tAC(min)  
tAC(min)  
2 x tCK +  
tAC(max)+1  
000  
2 x tCK +  
tAC(max)+1  
000  
2 x tCK +  
tAC(max)+1  
000  
tAC(min) +  
2000  
tAC(min) +  
2000  
tAC(min) +  
2000  
ODT turn-on (power-down mode)  
ODT turn-off (power-down mode)  
tAONPD  
tAQFPD  
ps  
ps  
2.5 x tCK +  
tAC(max)+1  
000  
2.5 x tCK +  
tAC(max)+1  
000  
2.5 x tCK +  
tAC(max)+1  
000  
tAC(min) +  
2000  
tAC(min) +  
2000  
tAC(min) +  
2000  
ODT to power-down entry latency  
tANPD  
tAXPD  
tMOD  
tXARD  
tSARDS  
tXP  
3
8
3
8
3
8
tCK  
tCK  
ns  
ODT power-down exit latency  
ODT enable from MRS command  
12  
2
12  
2
12  
2
Exit active POWER-DOWN to READ command, MR[12]=0  
Exit active POWER-DOWN to READ command, MR[12]=1  
Exit PRECHARGE POWER-DOWN to any non READ  
CKE Min. HIGH/LOW time  
tCK  
tCK  
tCK  
tCK  
7 - AL  
2
6 - AL  
2
6 - AL  
2
tCLE  
3
3
3
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR232M64PBG  
Rev. 1.3 6/09  
25  
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