i PEM
2.1 Gb SDRAM-DDR2
Gb
Austin Semiconductor, Inc.
AS4DDR232M64PBG
FIGURE 4 - POWER-UP AND INITIALIZATION
Notes appear on page 7
V
CC
V
CC
Q
V
TT1
V
REF
T0
tCK
Ta0
Tb 0
Tc0
Td 0
Te0
Tf 0
Tg 0
Th 0
Ti 0
Tj 0
Tk 0
Tl 0
Tm 0
t
VTD
1
CK#
CK
tCL
tCL
See
not e
3
SSTL_18
LVCM OS
CKE LOW LEVEL
8
LOW LEVEL
8
ODT
COM M A ND
NOP2
PRE
LM
LM
LM
LM
PRE
REF
REF
LM
LM
LM
VA LID
3
DM
7
A DDRESS
9
A 10 = 1
CODE
CODE
CODE
CODE
A 10 = 1
CODE
CODE
CODE
VA LID
DQS
7
DQ
7
R
TT
Hi g h -Z
Hi g h -Z
Hi g h -Z
T = 200μ s (M IN)
Po w er -u p :
V
CC
an d st ab l e
cl o ck (CK, CK#)
T = 400n s
(M IN)
t
RPA
EM R(2)
t M RD
t M RD
EM R(3)
t M RD
t M RD
t
RPA
t RFC
t RFC
See not e 4
t M RD
t M RD
t M RD
EM R w i t h
DLL ENA BLE
5
EM R w i t h
M R w /o
DLL RESET OCD Def au l t 10
200 cycl es o f CK3
EM R w i t h
OCD Exi t 11
No r m a l
Op er at i o n
DON’ T CA RE
In d i cat es a b r eak i n
t i m e scal e
M R w it h
DLL RESET
AS4DDR232M64PBG
Rev. 1.3 6/09
Austin Semiconductor, Inc.
●
Austin, Texas
●
512.339.1188
●
www.austinsemiconductor.com
6