i PEM
1.2 Gb SDRAM-DDR
Gb
Austin Semiconductor, Inc.
AS4DDR16M72PBG
TRUTH TABLE - COMMANDS (NOTE 1)
NAME (FUNCTION)
DESELECT (NOP)(9)
NO OPERATION (NOP) (9)
ACTIVE (Select bank and activate row) (3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE (8)
PRECHARGE (Deactivate row in bank or banks) (5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6,7)
LOAD MODE REGISTER (2)
CS#
H
L
L
L
L
L
L
L
L
RAS#
X
H
L
H
H
H
L
L
L
CAS#
X
H
H
L
L
H
H
L
L
WE#
X
H
H
H
L
L
L
H
L
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
Op-Code
TRUTH TABLE - DM OPERATION
NAME (FUNCTION)
WRITE ENABLE (10)
WRITE INHIBIT (10)
NOTES:
1 . CKE is HIGH for all commands shown except SELF REFRESH.
2 . A0-12 define the op-code to be written to the selected Mode Register.
BA0, BA1 select either the mode register (0, 0) or the extended mode
register (1, 0).
3. A0-12 provide row address, and BA0, BA1 provide bank address.
4. A0-8 provide column address; A10 HIGH enables the auto precharge
feature (non-persistent), while A10 LOW disables the auto precharge
feature; BA0, BA1 provide bank address.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH:
All banks precharged and BA0, BA1 are “Don’t Care.”
DM
L
H
DQs
Valid
X
6 . This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if
CKE is LOW.
7 . Internal refresh counter controls row addressing; all inputs and I/Os are
“Don’t Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command
is undefined (and should not be used) for READ bursts with auto
precharge enabled and for WRITE bursts.
9 . DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding
data.
READ
The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-8 selects
the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses.
PRECHARGE
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a
specified time (t
RP
) after the PRECHARGE command is
issued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer in
the current bank and does not violate any other timing
parameters. Input A10 determines whether one or all banks
are to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands being
issued to that bank. A PRECHARGE command will be treated
as a NOP if there is no open row in that bank (idle state), or
if the previously open row is already in the process of
precharging.
WRITE
The WRITE command is used to initiate a burst write access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-8 selects
the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the D/Qs
iswritten to the memory array subject to the DQM input logic
level appearing coincident with the data. If a given DQM signal
is registered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the
corresponding data inputs will be ignored, and a WRITE will
not be executed to that byte/column location.
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
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