i PEM
1.2 Gb SDRAM-DDR
Gb
Austin Semiconductor, Inc.
AS4DDR16M72PBG
GENERAL DESCRIPTION
The 1.2Gb DDR SDRAM MCM, is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM. Each of the chip’s 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.
The 128MB(1.2Gb) DDR SDRAM MCM uses a DDR
architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for
the 128MB DDR SDRAM effectively consists of a single 2n-
bit wide, one-clock-cycle data tansfer at the internal DRAM
core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during READs
and by the memory contoller during WRITEs. DQS is
edgealigned with data for READs and center-aligned with
data for WRITEs. Each chip has two data strobes, one for
the lower byte and one for the upper byte.
The 128MB DDR SDRAM operates from a differential clock
(CLK and CLK#); the crossing of CLK going HIGH and CLK#
going LOW will be referred to as the positive edge of CLK.
Commands (address and control signals) are registered
at every positive edge of CLK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be
accessed. The address bits registered coincident with the
READ or WRITE command are used to select the bank and
the starting column location for the burst access.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0 and
BA1 select the bank, A0-12 select the row). The address bits
registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The
following sections provide detailed information covering device
initialization, register defi nition, command descriptions and
device operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than those
specified may result in undefined operation. Power must first
be applied to V
CC
and V
CCQ
simultaneously, and then to V
REF
(and to the system V
TT
). V
TT
must be applied after V
CCQ
to avoid
device latch-up, which may cause permanent damage to the
device. V
REF
can be applied any time after V
CCQ
but is expected
to be nominally coincident with V
TT
. Except for CKE, inputs are
not recognized as valid until after V
REF
is applied. CKE is an
SSTL_2 input but will detect an LVCMOS LOW level after V
CC
is
applied. Maintaining an LVCMOS LOW level on CKE during
powerup is required to ensure that the DQ and DQS outputs
will be in the High-Z state, where they will remain until driven in
normal operation (by a read access). After all power supply and
reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200µs delay prior to applying an executable
command.
Once the 200µs delay has been satisfied, a DESELECT or
NOP command should be applied, and CKE should be brought
HIGH. Following the NOP command, a PRECHARGE ALL
command should be applied. Next a LOAD MODE REGISTER
command should be issued for the extended mode register
(BA1 LOW and BA0 HIGH) to enable the DLL, followed by another
LOAD MODE REGISTER command to the mode register (BA0/
BA1 both LOW) to reset the DLL and to program the operating
The DDR SDRAM provides for programmable READ or parameters. Two-hundred clock cycles are required between
WRITE burst lengths of 2, 4, or 8 locations. An auto precharge the DLL reset and any READ command. A PRECHARGE ALL
function may be enabled to provide a selftimed row command should then be applied, placing the device in the all
precharge that is initiated at the end of the burst access.
banks idle state.
The pipelined, multibank architecture of DDR SDRAMs allows Once in the idle state, two AUTO REFRESH cycles must be
for concurrent operation, thereby providing high effective performed (t
RFC
must be satisfi ed.) Additionally, a LOAD MODE
bandwidth by hiding row precharge and activation time.
REGISTER command for the mode register with the reset DLL
bit deactivated (i.e., to program operating parameters without
An auto refresh mode is provided, along with a powersaving resetting
the
DLL)
is
required.
Following
power-down mode.
these requirements, the DDR SDRAM is ready for normal
operation.
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AUSTIN [ AUSTIN SEMICONDUCTOR ]
