Meg
16 Me g FPM DRAM
Austin Semiconductor, Inc.
TEST MODE CYCLE
11
-60
SYMBOL
t
RC
t
RWC
t
RAC
t
CAC
t
AA
t
RAS
t
CAS
t
RSH
t
CSH
t
RAL
t
CWD
t
RWD
t
AWD
t
CPWD
t
PC
t
PRWC
t
RASP
t
CPA
t
OEA
t
OED
t
OEH
PARAMETER
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS\
Access time from CAS\
Access time from column address
RAS\ pulse width
CAS\ pulse width
RAS\ hold time
CAS\ hold time
Column address to RAS\ lead time
CAS\ to W\ delay time
RAS\ to W\ delay time
Column address to W\ delay time
CAS\ precharge to W\ delay time
Fast Page cycle time
Fast Page read-modify-write time
RAS\ pulse width (Fast Page Cycle)
Access time from CAS\ precharge
OE\ access time
OE\ to data delay
OE\ command hold time
20
20
65
20
20
65
35
45
90
60
65
45
90
65
100K
40
20
22
22
MIN
115
160
65
20
35
10K
10K
75
25
22
70
40
48
100
70
70
50
100
75
100K
45
22
MAX
MIN
135
180
70
22
38
10K
10K
-70
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
7
7
7
3, 4, 10, 12
3, 4, 5, 12
3, 10 ,12
NOTES
AS4C4M4
NOTES:
1. An initial pause of 200us is required after power-up followed by an 8 RAS\-only refresh or CAS\-before-RAS\ refresh cycles
before proper device operation is achieved.
2. V
IH
(MIN) and V
IL
(MAX) are reference levels for measuring timing of input signals. Transition times are measured between
V
IH
(MIN) and V
IL
(MAX) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the t
RCD
(MAX) limit insures that t
RAC
(MAX) and be met. t
RCD
(MAX) is specified as a reference point only.
If t
RCD
is greater than the specified t
RCD
(MAX) limit, then access time is controlled exclusively by t
CAC
.
5. Assumes that t
RCD
> t
RCD
(MAX).
6. t
OFF
(MIN) and t
OEZ
(MAX) define the time at which the output achieves the open circuit condition and are not referenced V
OH
or V
OL
.
7. t
WCS
, t
RWD
, t
CWD
and t
AWD
are non restrictive operating parameters. They are included in the data sheet as electrical character-
istics only. If t
WCS
> t
WCS
(MIN), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If t
CWD
> t
CWD
(MIN), t
RWD
> t
RWD
(MIN) and t
AWD
> t
AWD
(MIN), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
(Continued on page 7)
AS4C4M4
Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
AUSTIN [ AUSTIN SEMICONDUCTOR ]
