FLASH
AS29F010
Austin Semiconductor, Inc.
FIGURE 7: TEST CONDITIONS,
Test Setup
TABLE 6: TEST CONDITIONS,
Test Specifications
CONDITIONS
Output Load
ALL SPEEDS
UNIT
1 TTL Gate
Output Load Capacitance, C
(including jig capacitance)
L
50
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0/3
Input timing measurement
reference levels
Output timing measurement
reference levels
1.5
1.5
V
V
AC CHARACTERISTICS: Read-Only Operations
SYMBOL
SPEED OPTIONS
PARAMETER
JEDEC Std
TEST SETUP
MIN
-50
-60
-70
90
-120 -150 UNITS
1
t
t
50
60
70
90
120
150
ns
Read Cycle Time
AVAV
AVQV
RC
CE\ = V
IL
Address to Output Delay
t
t
MAX
50
60
70
90
120 150
ns
ACC
OE\ = V
IL
IL
Chip Enable to Output Delay
Output Enable to Output Delay
t
t
OE\ = V
MAX
MAX
MAX
MAX
MIN
50
25
15
15
60
30
20
20
70
35
20
20
90
40
25
25
120 150
ns
ns
ns
ns
ns
ELQV
GLQV
EHQZ
CE
t
t
t
t
50
30
30
55
35
35
OE
1
t
t
Chip Enable to Output High Z
DF
1
Output Enable to Output High Z
GHQZ
DF
0
Read
1
t
Output Enable Hold Time
OEH
Toggle and
Data Polling
10
MIN
MIN
ns
ns
Output Hold Time From Addresses
CE\ or OE\, Whichever Occurs
First
0
t
t
OH
AXQX
NOTES:
±. Npa ±00ꢀ aeꢃaed.
2. See Figsꢂe 7 rnd Trble 6 fpꢂ aeꢃa ꢃꢁecificraipnꢃ.
AS29F010
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 2.3 12/08
14
AUSTIN [ AUSTIN SEMICONDUCTOR ]
