FLASH
AS29F010
Austin Semiconductor, Inc.
erase circuits are disabled, and the device resets. Subsequent
writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent device power-up. No commands are required to retrieve data.
Reading Array Data
The device is automatically set to reading array data after
The device is also ready to read array data after completing an
Embedded Program or Embedded Erase algorithm.
unintentional writes when VCC is greater than VLKO
.
The system must issue the reset command to re-enable the
device for reading array data if DQ5 goes high, or while in the
autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information. The
Read Operations table provides the read parameters, and the
Read Operation Timings diagram shows the timing diagram.
Write Pulse “Glitch” Protection
Noise pulses of less than 5ns (typical) on OE\, CE\, or WE\
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE\ = VIL,
CE\ = VIH or WE\ = VIH. To initiate a write cycle, CE\ and WE\
must be a logical zero while OE\ is a logical one.
Reset Command
Writing the reset command to the device resets the device
to reading array data. Address bits are don’t care for this
command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing begins.
This resets the device to reading array data. Once erasure
begins, however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before programming
begins. This resets the device to reading array data. Once
programming begins, however, the device ignores reset com-
mands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to return
to reading array data.
Power-Up Write Inhibit
If WE\ = CE\ = VIL and OE\ = VIH during power up, the
device does not accept commands on the rising edge of WE\.
The internal state machine is automatically reset to reading
array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register command
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device to
reading array data.
All addresses are latched on the falling edge of WE\ or
CE\, whichever happens first. Refer to the appropriate timing
diagrams in the “AC Characteristics” section.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array
data.
TABLE 3: Autoselect Codes (High Voltage Method)
A8
to
A7
A5
to
A2
A16 to A13 to
A14 A10
DESCRIPTION
CE\
OE\ WE\
A9
A6
A1
A0 DQ7 to DQ0
Manufacturer ID
Device ID
L
L
L
L
H
H
X
X
X
X
V
V
X
X
L
L
X
X
L
L
L
01h
20h
ID
H
ID
01h
(protected)
Sector Protection
Verification
L
L
H
SA
X
V
X
L
X
H
L
ID
00h
(unprotected)
NOTE: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t Care
AS29F010
Rev. 0.3 10/02
6
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
AUSTIN [ AUSTIN SEMICONDUCTOR ]
