UVEPROM
Austin Semiconductor, Inc.
READ/OUTPUT DISABLE
When the outputs of two or more SMJ27C010As are
connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no
interference from competing outputs of the other devices. To
read the output of a single device, a low level signal is applied
to the E\ and G\ pins. All other devices in the circuit should
have their outputs disabled by applying a high-level signal to
one of these pins.
SMJ27C010A
AS27C010A
SNAP! PULSE PROGRAMMING
The SMJ27C010A is programmed by using the SNAP! Pulse
programming algorithm as illustrated by the flow chart
(Figure 1). This algorithm programs in a nominal time of
thirteen seconds. Actual programming time varies as a
function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse
of 100 microseconds (µs) followed by a byte verification to
determine when the addressed byte has been successfully
programmed. Up to ten 100µs pulses per byte are provided
before a failure is recognized.
The programming mode is achieved when V
PP
= 13V,
V
CC
= 6.5V, E\ = V
IL
, and G\ = V
IH
. Data is presented in
parallel (eight bits) on pins DQ0 through DQ7. Once addresses
and data are stable, PGM\ is pulsed low.
More than one device can be programmed when the devices
are connected in parallel. Locations can be programmed in
any order. When the SNAP! Pulse programming routine is
complete, all bits are verified with V
CC
= V
PP
= 5V ± 10%.
LATCHUP IMMUNITY
Latchup immunity on the SMJ27C010A is a minimum of
250mA on all inputs and outputs. This feature provides latchup
immunity beyond any potential transients at the printed
circuit board level when the devices are interfaced to
industry-standard TTL or MOS logic devices. The input/
output layout approach controls latchup without
compromising performance or packing density.
POWER DOWN
Active I
CC
supply current can be reduced from 30mA to 500µA
by applying a high TTL input on E\ and to 100µA by applying a
high CMOS input on E\. In this mode all outputs are in the
high-impedance state.
PROGRAM INHIBIT
Programming can be inhibited by maintaining high level
inputs on the E\ or the PGM\ pins.
ERASURE
Before programming, the SMJ27C010A EPROM is erased
by exposing the chip through the transparent lid to a high-
intensity ultraviolet light (wavelength 2537 Å). The
recommended minimum exposure dose (UV intensity x
exposure time) is 15-W
.
s/cm
2
. A typical 12-mW/cm
2
,
filterless UV lamp erases the device in 21 minutes. The lamp
should be located about 2.5cm above the chip during erasure.
After erasure, all bits are in the high state. It should be noted
that normal ambient light contains the correct wavelength for
erasure; therefore, when using the SMJ27C010A, the window
should be covered with an opaque label. After erasure (all
bits in logic high state), logic lows are programmed into the
desired locations. A programmed low can be erased only by
ultraviolet light.
PROGRAM VERIFY
Programmed bits can be verified with V
PP
= 13V when
G\ = V
IL
, and E\ = V
IL
, and PGM\ = V
IH
.
SIGNATURE MODE
The signature mode provides access to a binary code
identifying the manufacturer and type. This mode is activated
when A9 (pin 26) is forced to 12V. Two identifier bytes are
accessed by toggling A0. All other addresses must be held
low. The signature code for these devices is 97D6. A0 low
selects the manufacturer’s code 97 (Hex), and A0 high
selects the device code D6 (Hex), as shown in Table 2.
TABLE 2. SIGNATURE MODES
IDENTIFIER*
MANUFACTURER CODE
DEVICE CODE
A0
V
IL
V
IH
DQ7
1
1
DQ6
0
1
DQ5
0
0
PINS
DQ4
DQ3
1
1
0
0
DQ2
1
1
DQ1
1
1
DQ0
1
0
HEX
97
D6
* E\ = G\ = V
IL
, A1 - A8 = V
IL
, A9 = V
H
, A10 - A16 = V
IL
, V
PP
= V
CC
.
SMJ27C010A
AS27C010A
Rev. 2.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
AUSTIN [ AUSTIN SEMICONDUCTOR ]
