AT90CAN128
TDI, JTAG Test Data In. Serial input data to be shifted in to the Instruction Register or
Data Register (scan chains). When the JTAG interface is enabled, this pin can not be
used as an I/O pin.
• TCK, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, input channel 6
.
TDO, JTAG Test Data Out. Serial output data from Instruction Register or Data Register.
When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TMS, ADC5 – Port F, Bit 5
ADC5, Analog to Digital Converter, input channel 5
.
TMS, JTAG Test mode Select. This pin is used for navigating through the TAP-controller
state machine. When the JTAG interface is enabled, this pin can not be used as an I/O
pin.
• TDO, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, input channel 4
.
TCK, JTAG Test Clock. JTAG operation is synchronous to TCK. When the JTAG inter-
face is enabled, this pin can not be used as an I/O pin.
• ADC3 – Port F, Bit 3
ADC3, Analog to Digital Converter, input channel 3.
• ADC2 – Port F, Bit 2
ADC2, Analog to Digital Converter, input channel 2.
• ADC1 – Port F, Bit 1
ADC1, Analog to Digital Converter, input channel 1.
• ADC0 – Port F, Bit 0
ADC0, Analog to Digital Converter, input channel 0.
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4250E–CAN–12/04
ATMEL [ ATMEL ]
