欢迎访问ic37.com |
会员登录 免费注册
发布采购

MEGA128CAN 参数 Datasheet PDF下载

MEGA128CAN图片预览
型号: MEGA128CAN
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器,带有ISP功能的Flash和CAN控制器128K字节 [Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER]
分类和应用: 微控制器
文件页数/大小: 413 页 / 5507 K
品牌: ATMEL [ ATMEL ]
 浏览型号MEGA128CAN的Datasheet PDF文件第203页浏览型号MEGA128CAN的Datasheet PDF文件第204页浏览型号MEGA128CAN的Datasheet PDF文件第205页浏览型号MEGA128CAN的Datasheet PDF文件第206页浏览型号MEGA128CAN的Datasheet PDF文件第208页浏览型号MEGA128CAN的Datasheet PDF文件第209页浏览型号MEGA128CAN的Datasheet PDF文件第210页浏览型号MEGA128CAN的Datasheet PDF文件第211页  
AT90CAN128  
TWI Register Description  
TWI Bit Rate Register – TWBR  
Bit  
7
TWBR7  
R/W  
0
6
TWBR6  
R/W  
0
5
TWBR5  
R/W  
0
4
TWBR4  
R/W  
0
3
TWBR3  
R/W  
0
2
TWBR2  
R/W  
0
1
TWBR1  
R/W  
0
0
TWBR0  
R/W  
0
TWBR  
Read/Write  
Initial Value  
• Bits 7..0 – TWI Bit Rate Register  
TWBR selects the division factor for the bit rate generator. The bit rate generator is a  
frequency divider which generates the SCL clock frequency in the Master modes. See  
“Bit Rate Generator Unit” on page 205 for calculating bit rates.  
TWI Control Register – TWCR  
Bit  
7
TWINT  
R/W  
0
6
TWEA  
R/W  
0
5
TWSTA  
R/W  
0
4
TWSTO  
R/W  
0
3
2
TWEN  
R/W  
0
1
0
TWIE  
R/W  
0
TWWC  
TWCR  
Read/Write  
Initial Value  
R
0
R
0
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to  
initiate a master access by applying a START condition to the bus, to generate a  
receiver acknowledge, to generate a stop condition, and to control halting of the bus  
while the data to be written to the bus are written to the TWDR. It also indicates a write  
collision if data is attempted written to TWDR while the register is inaccessible.  
• Bit 7 – TWINT: TWI Interrupt Flag  
This bit is set by hardware when the TWI has finished its current job and expects appli-  
cation software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will  
jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is  
stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note  
that this flag is not automatically cleared by hardware when executing the interrupt rou-  
tine. Also note that clearing this flag starts the operation of the TWI, so all accesses to  
the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Regis-  
ter (TWDR) must be complete before clearing this flag.  
• Bit 6 – TWEA: TWI Enable Acknowledge Bit  
The TWEA bit controls the generation of the ACK pulse. If the TWEA bit is written to  
one, the ACK pulse is generated on the TWI bus if the following conditions are met:  
1. The device’s own slave address has been received.  
2. A general call has been received, while the TWGCE bit in the TWAR is set.  
3. A data byte has been received in Master Receiver or Slave Receiver mode.  
By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-  
wire Serial Bus temporarily. Address recognition can then be resumed by writing the  
TWEA bit to one again.  
• Bit 5 – TWSTA: TWI START Condition Bit  
The application writes the TWSTA bit to one when it desires to become a master on the  
Two-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a  
START condition on the bus if it is free. However, if the bus is not free, the TWI waits  
until a STOP condition is detected, and then generates a new START condition to claim  
207  
4250E–CAN–12/04  
 复制成功!