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MEGA128CAN 参数 Datasheet PDF下载

MEGA128CAN图片预览
型号: MEGA128CAN
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器,带有ISP功能的Flash和CAN控制器128K字节 [Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER]
分类和应用: 微控制器
文件页数/大小: 413 页 / 5507 K
品牌: ATMEL [ ATMEL ]
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AT90CAN128  
Two-wire Serial Interface  
Features  
Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed  
Both Master and Slave Operation Supported  
Device can Operate as Transmitter or Receiver  
7-bit Address Space allows up to 128 Different Slave Addresses  
Multi-master Arbitration Support  
Up to 400 kHz Data Transfer Speed  
Slew-rate Limited Output Drivers  
Noise Suppression Circuitry Rejects Spikes on Bus Lines  
Fully Programmable Slave Address with General Call Support  
Address Recognition Causes Wake-up when AVR is in Sleep Mode  
Two-wire Serial Interface The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applica-  
tions. The TWI protocol allows the systems designer to interconnect up to 128 different  
Bus Definition  
devices using only two bi-directional bus lines, one for clock (SCL) and one for data  
(SDA). The only external hardware needed to implement the bus is a single pull-up  
resistor for each of the TWI bus lines. All devices connected to the bus have individual  
addresses, and mechanisms for resolving bus contention are inherent in the TWI  
protocol.  
Figure 90. TWI Bus Interconnection  
Device 1  
Device 3  
Device 2  
Device n  
........  
VCC  
R1  
R2  
SDA  
SCL  
TWI Terminology  
The following definitions are frequently encountered in this section.  
Table 88. TWI Terminology  
Term  
Description  
Master  
The device that initiates and terminates a transmission. The master also  
generates the SCL clock  
Slave  
The device addressed by a master  
Transmitter The device placing data on the bus  
Receiver The device reading data from the bus  
Electrical Interconnection  
As depicted in Figure 90, both bus lines are connected to the positive supply voltage  
through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or  
open-collector. This implements a wired-AND function which is essential to the opera-  
tion of the interface. A low level on a TWI bus line is generated when one or more TWI  
devices output a zero. A high level is output when all TWI devices tri-state their outputs,  
199  
4250E–CAN–12/04  
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