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MEGA128CAN 参数 Datasheet PDF下载

MEGA128CAN图片预览
型号: MEGA128CAN
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器,带有ISP功能的Flash和CAN控制器128K字节 [Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER]
分类和应用: 微控制器
文件页数/大小: 413 页 / 5507 K
品牌: ATMEL [ ATMEL ]
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Disabling the Receiver  
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from  
ongoing receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero)  
the Receiver will no longer override the normal function of the RxDn port pin. The  
Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in  
the buffer will be lost  
Flushing the Receive Buffer  
The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer  
will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed  
during normal operation, due to for instance an error condition, read the UDRn I/O loca-  
tion until the RXCn flag is cleared.  
The following code example shows how to flush the receive buffer.  
Assembly Code Example(1)  
USART0_Flush:  
lds  
r16, UCSR0A  
sbrs r16, RXC0  
ret  
lds  
r16, UDR0  
rjmp USART0_Flush  
C Code Example(1)  
void USART0_Flush (void )  
{
unsigned char dummy;  
while (UCSR0A & (1<<RXC0) ) dummy = UDR0;  
}
Note:  
1. The example code assumes that the part specific header file is included.  
Asynchronous Data  
Reception  
The USARTn includes a clock recovery and a data recovery unit for handling asynchro-  
nous data reception. The clock recovery logic is used for synchronizing the internally  
generated baud rate clock to the incoming asynchronous serial frames at the RxDn pin.  
The data recovery logic samples and low pass filters each incoming bit, thereby improv-  
ing the noise immunity of the Receiver. The asynchronous reception operational range  
depends on the accuracy of the internal baud rate clock, the rate of the incoming  
frames, and the frame size in number of bits.  
Asynchronous Clock  
Recovery  
The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig-  
ure 87 illustrates the sampling process of the start bit of an incoming frame. The sample  
rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double  
Speed mode. The horizontal arrows illustrate the synchronization variation due to the  
sampling process. Note the larger time variation when using the Double Speed mode  
(U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line  
is idle (i.e., no communication activity).  
184  
AT90CAN128  
4250E–CAN–12/04  
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