Serial Peripheral Interface – SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the AT90CAN128 and peripheral devices or between several AVR devices.
The AT90CAN128 SPI includes the following features:
Features
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Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
Figure 79. SPI Block Diagram(1)
clkIO
DIVIDER
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Note:
1. Refer to Figure 2 on page 4, and Table 32 on page 71 for SPI pin placement.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 80.
The system consists of two shift Registers, and a Master clock generator. The SPI Mas-
ter initiates the communication cycle when pulling low the Slave Select SS pin of the
desired Slave. Master and Slave prepare the data to be sent in their respective shift
Registers, and the Master generates the required clock pulses on the SCK line to inter-
162
AT90CAN128
4250E–CAN–12/04
ATMEL [ ATMEL ]
