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ATMEGA64A-AU 参数 Datasheet PDF下载

ATMEGA64A-AU图片预览
型号: ATMEGA64A-AU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有64K字节的系统内可编程闪存 [8-bit Microcontroller with 64K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 7964 K
品牌: ATMEL [ ATMEL ]
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ATmega64A  
0x0012  
0x0014  
0x0016  
0x0018  
0x001A  
0x001C  
0x001E  
0x0020  
0x0022  
0x0024  
0x0026  
0x0028  
0x002A  
0x002C  
0x002E  
0x0030  
0x0032  
0x0034  
0x0036  
0x0038  
0x003A  
0x003C  
0x003E  
0x0040  
0x0042  
0x0044  
;
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
jmp  
TIM2_COMP  
TIM2_OVF  
TIM1_CAPT  
TIM1_COMPA  
TIM1_COMPB  
TIM1_OVF  
TIM0_COMP  
TIM0_OVF  
SPI_STC  
; Timer2 Compare Handler  
; Timer2 Overflow Handler  
; Timer1 Capture Handler  
; Timer1 CompareA Handler  
; Timer1 CompareB Handler  
; Timer1 Overflow Handler  
; Timer0 Compare Handler  
; Timer0 Overflow Handler  
; SPI Transfer Complete Handler  
; USART0 RX Complete Handler  
; USART0,UDR Empty Handler  
; USART0 TX Complete Handler  
; ADC Conversion Complete Handler  
; EEPROM Ready Handler  
USART0_RXC  
USART0_DRE  
USART0_TXC  
ADC  
EE_RDY  
ANA_COMP  
TIM1_COMPC  
TIM3_CAPT  
TIM3_COMPA  
TIM3_COMPB  
TIM3_COMPC  
TIM3_OVF  
USART1_RXC  
USART1_DRE  
USART1_TXC  
TWI  
; Analog Comparator Handler  
; Timer1 CompareC Handler  
; Timer3 Capture Handler  
; Timer3 CompareA Handler  
; Timer3 CompareB Handler  
; Timer3 CompareC Handler  
; Timer3 Overflow Handler  
; USART1 RX Complete Handler  
; USART1,UDR Empty Handler  
; USART1 TX Complete Handler  
; Two-wire Serial Interface Handler  
; SPM Ready Handler  
SPM_RDY  
0x0046 RESET: ldi  
r16, high(RAMEND); Main program start  
0x0047  
0x0048  
out  
ldi  
SPH,r16  
; Set Stack Pointer to top of RAM  
r16, low(RAMEND)  
0x0049  
0x004A  
out  
sei  
SPL,r16  
; Enable interrupts  
0x004B  
:.  
<instr> xxx  
:. :.  
:.  
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and the  
IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and  
general program setup for the Reset and Interrupt Vector Addresses is:  
AddressLabels Code  
0x0000 RESET: ldi  
Comments  
r16,high(RAMEND); Main program start  
0x0001  
0x0002  
out  
ldi  
SPH,r16  
; Set Stack Pointer to top of RAM  
r16,low(RAMEND)  
SPL,r16  
0x0003  
0x0004  
out  
sei  
; Enable interrupts  
0x0005  
;
<instr> xxx  
.org 0x7002  
0x7002  
0x7004  
:.  
jmp  
jmp  
:.  
EXT_INT0  
; IRQ0 Handler  
; IRQ1 Handler  
;
EXT_INT1  
:.  
0x7044  
jmp  
SPM_RDY ; Store Program Memory Ready Handler  
62  
8160C–AVR–07/09  
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