ATmega64A
23.5
23.6
23.7
23.8
23.9
Prescaling and Conversion Timing ................................................................236
Changing Channel or Reference Selection ...................................................239
ADC Noise Canceler .....................................................................................241
ADC Conversion Result .................................................................................245
Register Description ......................................................................................247
24 JTAG Interface and On-chip Debug System ...................................... 252
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
24.9
Features ........................................................................................................252
Overview ........................................................................................................252
TAP – Test Access Port ................................................................................252
TAP Controller ...............................................................................................255
Using the Boundary -scan Chain ...................................................................256
Using the On-chip Debug system ..................................................................256
On-chip Debug Specific JTAG Instructions ...................................................257
Using the JTAG Programming Capabilities ...................................................258
On-chip Debug Related Register in I/O Memory ...........................................258
24.10 Bibliography ...................................................................................................258
25 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 259
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
Features ........................................................................................................259
Overview ........................................................................................................259
Data Registers ...............................................................................................259
Boundary-scan Specific JTAG Instructions ...................................................261
Boundary-scan Chain ....................................................................................262
ATmega64A Boundary-scan Order ...............................................................273
Boundary-scan Description Language Files ..................................................280
Boundary-scan Related Register in I/O Memory ...........................................280
26 Boot Loader Support – Read-While-Write Self-programming ......... 281
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
Features ........................................................................................................281
Overview ........................................................................................................281
Application and Boot Loader Flash Sections .................................................281
Read-While-Write and No Read-While-Write Flash Sections ........................282
Boot Loader Lock Bits ...................................................................................284
Entering the Boot Loader Program ................................................................285
Addressing the Flash During Self-programming ............................................286
Self-programming the Flash ..........................................................................287
Register Description ......................................................................................293
v
8160C–AVR–07/09
ATMEL [ ATMEL ]
