ATmega64A
Table 28-15. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
4 MHz Oscillator Variable Oscillator
Symbol
Parameter
Min
Max
Min
Max
8
Unit
MHz
ns
0
1/tCLCL
Oscillator Frequency
Read Low to Data Valid
RD Pulse Width
0.0
10 tRLDV
12 tRLRH
14 tWHDX
15 tDVWH
16 tWLWH
690
3.0tCLCL-60
735
485
750
735
3.0tCLCL-15
2.0tCLCL-15
3.0tCLCL
ns
Data Hold After WR High
Data Valid to WR High
WR Pulse Width
ns
ns
3.0tCLCL-15
ns
Figure 28-6. External Memory Timing (SRWn1 = 0, SRWn0 = 0
T1
T2
T3
T4
System Clock (CLKCPU
)
1
ALE
4
2
7
A15:8 Prev. addr.
Address
15
3a
3b
13
DA7:0 Prev. data
Address
6
XX
Data
16
14
WR
9
11
DA7:0 (XMBK = 0)
Address
5
Data
10
8
12
RD
340
8160C–AVR–07/09
ATMEL [ ATMEL ]
